KR19990072029A - 마이크로웨이브 하이브리드 집적회로 - Google Patents

마이크로웨이브 하이브리드 집적회로 Download PDF

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Publication number
KR19990072029A
KR19990072029A KR1019980704323A KR19980704323A KR19990072029A KR 19990072029 A KR19990072029 A KR 19990072029A KR 1019980704323 A KR1019980704323 A KR 1019980704323A KR 19980704323 A KR19980704323 A KR 19980704323A KR 19990072029 A KR19990072029 A KR 19990072029A
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South Korea
Prior art keywords
dielectric plate
integrated circuit
hybrid integrated
recess
pattern layer
Prior art date
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KR1019980704323A
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English (en)
Inventor
빅토르 아나톨례비치 이오브달스키
Original Assignee
윤종용
삼성전자 주식회사
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Application filed by 윤종용, 삼성전자 주식회사 filed Critical 윤종용
Publication of KR19990072029A publication Critical patent/KR19990072029A/ko

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Materials Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Combinations Of Printed Boards (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Waveguides (AREA)
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Abstract

본 발명에 따른 마이크로웨이브 하이브리드 집적회로는 위상 금속화 패턴층(2)과 반도체칩(5)이 고착제(4)로 고착되는 공간인 다수의 리세스(3)를 구비한 유전체판(1)을 포함한다. 접촉패드(6)를 구비한 상기 칩(5)의 표면은 상기 유전체판(1)의 표면과 동일평면상에 위치하고 상기 칩(5)의 접촉패드(6)는 상기 위상 금속화 패턴층(2)에 전기적으로 연결된다. 상기 리세스(3)의 벽은 상기 유전체판(1)의 평면을 향해 90.1-150。 각도(α)로 경사지게 형성된다.

Description

마이크로웨이브 하이브리드 집적회로
이미 기술적으로 공지된 마이크로웨이브 하이브리드 집적회로(IC)는 위상 금속화 패턴층을 구비한 유전체판 및, 상기 위상 금속화 패턴층에 전기적으로 연결되는 접촉패드를 갖는 각 칩의 표면이 기판표면과 동일평면에 위치하도록 상기 기판속에 배치되는 반도체칩을 포함한다(US,A,4,722,914).
그러나, 전술한 형태의 하이브리드 집적회로는 리세스의 벽들중 하나로 부터 다른 벽을 향해 상기 리세스의 저부를 따라 상기 반도체칩의 변위 가능성으로 인한 상호연결 와이어의 길이에 있어서의 가변성때문에 야기되는 회로의 전기적 파라미터가 분산되는 문제점이 있었다.
이미 공지된 또다른 형태의 마이크로웨이브 하이브리드 집적회로는 위상 금속화 패턴층과 다수의 리세스를 구비하는 유전체판을 포함하는데, 상기 집적회로에 있어서, 칩-형태의 반도체 장치의 칩들은, 상기 위상 금속화 패턴층에 전기적으로 연결되는 접촉패드를 갖는 칩의 표면이 상기 유전체판의 표면과 동일평면에 위치하도록 고착제에 의해 고착된다(JP,B,49-12794).
그러나, 전술한 형태의 하이브리드 집적회로는 상호연결 와이어의 길이에 있어서의 가변성과 함께 칩을 정확히 장착하는 도중에 상기 리세스의 저부를 따라 칩이 변위됨으로 인한 전기적 파라미터의 재생능력이 저하되는 문제점이 있었다.
본 발명은 전자 공학, 특히 마이크로웨이브 하이브리드 집적회로(IC) (microwave hybrid integrated circuit)에 관한 것이다.
도 1은 본 발명의 제 1 실시예에 따른 마이크로웨이브 하이브리드 집적회로를 나타낸 종단면도이다.
도 2는 도 1의 평면도이다.
도 3은 본 발명의 제 2 실시예에 따른 마이크로웨이브 하이브리드 집적회로를 나타낸 종단면도이다.
도 4는 본 발명의 제 3 실시예에 따른 마이크로웨이브 하이브리드 집적회로를 나타낸 종단면도이다.
따라서, 본 발명의 목적은 상기 종래기술에 따른 문제점을 극복하고, 집적회로의 전기적 파라미터의 재생능력 및 제조능력을 향상시키기 위해, 반도체칩이 고착되는 공간인 리세스를 유전체판내부에 형성시킨 마이크로웨이브 하이브리드 집적회로를 제공하는데 있다.
상기 목적을 달성하기 위해, 본원 발명의 일면에 따라, 위상 금속화 패턴층과, 반도체칩이 고착제에 의해 고착되는 공간인 다수의 리세스를 구비한 유전체판을 포함하되, 상기 위상 금속화 패턴층에 전기적으로 연결되는 접촉패드를 구비한 상기 반도체칩의 표면이 상기 유전체판의 표면과 동일평면상에 위치하는 마이크로웨이브 하이브리드 집적회로가 제공되고, 상기 마이크로웨이브 하이브리드 집적회로는, 각각의 리세스의 벽이 상기 유전체판의 평면을 향해 90.1-150°각도로 경사지게 형성되는 것을 특징으로 한다.
상기 리세스 벽의 경사각도를 90.1。이하로 상기 유전체판의 평면을 향해 정하게 되면, 만족스런 결과를 얻지 못하는 한편, 상기 경사각도를 150。보다 크게 정하면, 연결 리드의 길이가 실질적으로 늘어나고, 그에 따라, 스퓨리어스 인덕턴스가 커지게 된다.
상기 리세스는 금속화될 수도 있고, 상기 금속화된 코팅층은 상기 유전체판의 상기 위상 금속화 패턴층에 전기적으로 연결될 수도 있다. 상기 유전체판은 그 배면상에 시일드 접지 금속화층을 구비할 수도 있고, 상기 리세스의 저부에는 상기 시일드 접지 금속화층과의 연결을 위해 전기 및 열전도 물질로 채워지는 금속화 구멍이 형성될 수도 있다.
상기 리세스 벽을 90.1-150°각도(α)로 상기 유전체판의 평면을 향해 경사지게 함으로써, 다음과 같은 장점을 얻을 수 있다.
첫째, 상기 리세스의 저부를 따라 칩의 변위 가능성을 억제할 수 있고, 그에 따라, 상기 접촉패드와 상기 위상 금속화 패턴층을 상호연결하는 도체의 길이의 가변성을 줄일수 있음으로 인하여, 회로의 전기적 파라미터의 재생능력이 향상된다.
둘째, 상기 리세스내에서의 상기 칩 장착 및 칩의 위치설정 정확도가 향상됨은 물론, 상기 금속화 리세스와 상기 위상 금속화 패턴층간의 전기적인 연결이 단순화됨으로써, 제조능력이 향상된다.
첨부도면을 참조하여, 실시예를 통해 본 발명이 이하에 상세히 설명된다.
첨부 도면에서, 동일한 참조 번호는 동일한 구성요소를 나타낸다.
본 발명의 제 1 실시예에 따른 마이크로웨이브 하이브리드 집적회로(IC)는 표면상에 위상 금속화 패턴층 2가 형성되고 Polcor로 제조되는 0.5mm 두께의 유전체판 1을 포함한다. 상기 위상 금속화 패턴층 2는 Cr-Cu 구조(분무-용착 기술에 의해 적용되는 3μm두께)-Cu(3μm두께로 전기도금됨)-Ni(0.5μm두께로 전기도금됨)-Au(3μm두께로 전기도금됨)로 구성될 수도 있다. 상기 유전체판 1은 상기 유전체판의 평면을 향해 내벽이 α=120。각도로 경사진 0.6×0.6×0.16mm 크기의 다수의 리세스 3을 구비한다. 이 경우, 상기 리세스의 저부에 형성되는 고착제층 4의 두께는 10μm이고, 상기 칩 5와 상기 리세스 3의 상부 가장자리사이의 간격은 87μm이다. ЭЧЭ-C 타입의 접착제(표준명세 ЬＩУО 0,028,052ТУ)가 상기 고착제 4로서 사용될 수도 있다.
0.5×0.5×0.15mm 크기의 칩 트랜지스터 3П325A-5형태의 상기 칩 5는 그 표면이 상기 유전체판 1의 표면과 일치하도록 상기 리세스 3속에 장착된다. 상기 칩 5의 접촉패드 6은 15μm 직경의 금제 와이어 7에 의해 상기 위상 금속화 패턴층 2에 전기적으로 연결된다.
상기 리세스 3(도 3 참조)은 금속-코팅될 수도 있고, 상기 금속코팅층의 구조는 예컨대, Pd-Ni(0.2μm 두께로 화학적으로 용착됨)-Cu(3μm 두께로 전기도금됨)-Ni(0.5μm 두께로 전기도금됨)-Au(3μm두께로 전기도금됨)로 구성될 수도 있다.
도 4에 도시된 바와같이, 상기 리세스 3의 저부에는, 예컨대, PdCl2+SnCl2로 미리 활성화된 구리로 성장된 전기 및 열 전도물질 10으로 채워지는 100μm 직경의 금속화 구멍(9)이 형성된다. 상기 유전체판 1의 배면에는, 상기 유전체판 1의 표면상에 형성된 상기 위상 금속화 패턴층 2의 구조와 유사한 구조를 갖는 시일드 접지 금속화층 11이 형성된다.
본 발명에 따른 마이크로웨이브 하이브리드 집적회로는 다음과 같이 작용한다.
즉, 신호가 트랜지스터 증폭기단의 입력에 입력되어 적절한 변환을 거친후, 상기 증폭된 신호는 상기 트랜지스터 증폭기단의 출력에 보내진다.
본 발명에 따른 마이크로웨이브 하이브리드 집적회로를 사용하면, 반도체칩의 상호연결 와이어(리드)의 길이의 가변성을 줄임으로써 회로의 전기적 파라미터의 재생능력이 향상될 수 있고, 상기 리세스내에서의 칩 장착 및 칩의 위치설정이 보다 정확해지고 상기 금속화 리세스와 상기 위상 금속화 패턴층간의 전기적인 연결이 보다 단순화됨으로써, 제조능력이 향상된다. 결국, 상기 집적회로의 트리밍 공정작업이 수월해질수 있다.
더욱이, 상기 리세스의 금속화 및 상기 리세스의 상기 위상 금속화 패턴층과의 연결로 인하여, 상기 집적회로의 신뢰성이 향상된다.
본 발명에 따른 전술한 실시예들을 기술함에 있어서, 협의의 특정용어는 명료성 차원에서 사용된다. 그러나, 본 발명은 선택된 특정용어에 한정되는 것은 아니며, 그러한 각 용어들은 유사한 방식으로 작동하고 유사한 기술적 문제점의 해결을 위해 사용되는 모든 등가의 요소들을 포함한다는 것을 명심해야 한다.
지금까지, 특정의 바람직한 실시예및 그 대체 실시예와 관련하여 본 발명이 상세히 개시되고 설명되었지만, 상기 본 발명에 대한 개시는 단지 본 발명의 적용예에 불과한 것이고, 본 발명을 수행하기 위한 최상 모드로서 본 명세서에 개시된 특정 실시예에 국한되는 것은 아니다.
또한, 하기 특허청구의 범위에 의해 마련되는 본 발명의 사상이나 분야를 일탈하지 않는 범위내에서 본 발명이 다양하게 개조및 변경될 수 있다는 것을 당업계에서 통상의 지식을 가진자라면 용이하게 이해할 수 있을 것이다.
본 발명은 반도체 미소 전자공학(semiconductor microelectronics)분야에 사용될 수 있다.

Claims (3)

  1. 위상 금속화 패턴층(2) 및, 반도체칩(5)이 고착제(4)에 의해 고착되는 공간인 다수의 리세스(3)를 구비한 유전체판(1)을 포함하되, 상기 위상 금속화 패턴층(2)에 전기적으로 연결되는 접촉패드(6)를 구비한 상기 반도체칩의 표면이 상기 유전체판(1)의 표면과 동일평면상에 위치하는 마이크로웨이브 하이브리드 집적회로에 있어서,
    상기 각각의 리세스(3) 벽은 상기 유전체판(1)의 평면을 향해 90.1-150。 각도(α)로 경사지게 형성되는 것을 특징으로 하는 마이크로웨이브 하이브리드 집적회로.
  2. 제 1 항에 있어서, 상기 리세스(3)는 금속화되고, 상기 금속화된 리세스(3)는 상기 유전체판(1)의 상기 위상 금속화 패턴층(2)에 전기적으로 연결되는 것을 특징으로 하는 마이크로웨이브 하이브리드 집적회로.
  3. 제 1 항 또는 제 2 항에 있어서, 상기 유전체판(1)은 그 배면상에 시일드 접지 금속화층(11)을 구비하고, 상기 리세스(3)의 저부에는 전기 및 열전도 물질(10)로 채워지는 금속화 구멍(9)이 형성되는 것을 특징으로 하는 마이크로웨이브 하이브리드 집적회로.
KR1019980704323A 1996-10-10 1996-10-10 마이크로웨이브 하이브리드 집적회로 KR19990072029A (ko)

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Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6259148B1 (en) * 1998-08-13 2001-07-10 International Business Machines Corporation Modular high frequency integrated circuit structure
US6779733B2 (en) * 2000-02-22 2004-08-24 Toray Engineering Company, Limited Noncontact id card or the like and method of manufacturing the same
CN1421019A (zh) * 2000-04-04 2003-05-28 东丽工程株式会社 Cof组件的制造方法
DE10122221A1 (de) * 2001-05-08 2002-11-21 Danfoss Silicon Power Gmbh Leistungselektronikmodul mit einer Bodenplatte und darauf gelötetem Substrat
US6707150B1 (en) * 2002-10-24 2004-03-16 Galaxy Pcb Co., Ltd. Package support member with high heat-removing ability
JP3844467B2 (ja) 2003-01-08 2006-11-15 沖電気工業株式会社 半導体装置及びその製造方法
US7253735B2 (en) 2003-03-24 2007-08-07 Alien Technology Corporation RFID tags and processes for producing RFID tags
JP2004361308A (ja) * 2003-06-06 2004-12-24 Fuji Electric Device Technology Co Ltd 物理量検出装置および物理量検出手段格納ケース
DE102004016940B4 (de) * 2004-04-06 2019-08-08 Continental Automotive Gmbh Schaltungsträger für einen Halbleiterchip und ein Bauelement mit einem Halbleiterchip
US7688206B2 (en) 2004-11-22 2010-03-30 Alien Technology Corporation Radio frequency identification (RFID) tag for an item having a conductive layer included or attached
US9704809B2 (en) * 2013-03-05 2017-07-11 Maxim Integrated Products, Inc. Fan-out and heterogeneous packaging of electronic components
CN105140189B (zh) * 2015-07-08 2019-04-26 华进半导体封装先导技术研发中心有限公司 板级扇出型芯片封装器件及其制备方法
CN113359248B (zh) * 2021-06-02 2022-11-15 青岛海信宽带多媒体技术有限公司 一种光模块

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52127177A (en) * 1976-04-19 1977-10-25 Toshiba Corp Semiconductor device
JPS59182545A (ja) * 1983-03-31 1984-10-17 Nec Home Electronics Ltd 混成集積回路
JPS63271944A (ja) * 1987-04-28 1988-11-09 Sumitomo Electric Ind Ltd 半導体装置
JP3190057B2 (ja) * 1990-07-02 2001-07-16 株式会社東芝 複合集積回路装置
RU2025822C1 (ru) * 1991-03-19 1994-12-30 Государственное научно-производственное предприятие "Исток" Гибридная интегральная схема
RU2004036C1 (ru) * 1991-04-25 1993-11-30 Виктор Анатольевич Иовдальский Гибридна интегральна СВЧ- и КВЧ-схема
DE4222474A1 (de) * 1992-07-09 1994-01-13 Bosch Gmbh Robert Montageeinheit für Mehrlagenhybrid mit Leistungsbauelementen
JPH06132417A (ja) * 1992-10-20 1994-05-13 Fujitsu Ltd 超高周波装置
JPH0810739B2 (ja) * 1993-02-08 1996-01-31 日本電気株式会社 ハイブリッドｉｃ
JP3292798B2 (ja) * 1995-10-04 2002-06-17 三菱電機株式会社 半導体装置

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SE9801988L (sv) 1998-06-04
US6204555B1 (en) 2001-03-20
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SE9801988D0 (sv) 1998-06-04
JP2000516044A (ja) 2000-11-28
WO1998015981A1 (fr) 1998-04-16

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