SE522105C2 - Integrerad mikrovåghybridkrets - Google Patents

Integrerad mikrovåghybridkrets

Info

Publication number
SE522105C2
SE522105C2 SE9801988A SE9801988A SE522105C2 SE 522105 C2 SE522105 C2 SE 522105C2 SE 9801988 A SE9801988 A SE 9801988A SE 9801988 A SE9801988 A SE 9801988A SE 522105 C2 SE522105 C2 SE 522105C2
Authority
SE
Sweden
Prior art keywords
recess
hybrid circuit
topological
metallization
microwave hybrid
Prior art date
Application number
SE9801988A
Other languages
English (en)
Other versions
SE9801988L (sv
SE9801988D0 (sv
Inventor
Viktor Anatolievich Iovdalsky
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of SE9801988L publication Critical patent/SE9801988L/sv
Publication of SE9801988D0 publication Critical patent/SE9801988D0/sv
Publication of SE522105C2 publication Critical patent/SE522105C2/sv

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48101—Connecting bonding areas at the same height, e.g. horizontal bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Description

.ii-i 10 15 20 25 30 522 105 2 Om väggamas lutningsvinkel mot kortytans plan görs mindre än 90,l° erhålls inte något positivt resultat och om nämnda vinkel görs större än lS0° förlängs väsentligen längden av anslutningstrådar och följaktligen den icke önskade induktansen.
Urtagníngarna kan metalliseras och metallbeläggningen kan anslutas elektriskt till kortets topologiska metallisering. Kortet kan förses med skärmjordningsmetalliseringen på sin baksida och i botten av uitagningarna kan de metalliserade hålen göras, fyllas med ett elektriskt och värmeledande material, för anslutning till skärmjordningsmetalliseringen.
Genom att utföra urtagningamas väggar lutande mot koitytans plan vid en vinkel ot=90,l-150° säkerställs: - för det första att möjligheten för chipsförskjutning utmed botten av urtagningama begränsas och att följaktligen variationen av längden hos ledare, som hopkopplar kontaktplattorna med den topologiska metalliseringen minskas, varigenom reproducerbarheten av kretsens elektriska parametrar ökas; - för det andra att noggrannheten beträffande chipsinpassningen i urtagningen samt orienteringen av chipset däri ökas samt att den elektriska anslutningen mellan metallisering i urtagningen och den topologiska metalliseringen förenklas, varigenom producerbarheten ökas.
Kort beskrivning av ritningarna Föreliggande uppfinning åskådliggörs genom en detaljerad beskrivning av några specifika såsom exempel angivna utföringsformer av densamma under hänvisning till de bifogade ritningarna, van/id: fig. 1 visar en sektionsvy av den nya integrerade mikrovåghybridkretsen; fig. 2 visar en planvy av fig. 1; fig. 3 visar en sektionsvy av en annan utföringsform av den nya integrerade mikrovåghybridkretsen; och fig. 4 visar en sektionsvy av ännu en utföringsform av den nya integrerade mikrovåghybridlqetsen.
Bästa förfarande för att förverkliga uppfinningen Den integrerade mikrovághybridkretsen enligt uppfinningen innefattar ett 0,5 mm tjockt dielektriskt kort 1 (fig. 1 och 2), som är tillverkat av exempelvis Polycor och har ett topologiskt metalliseringsmönster 2 på sin framsida. Den topologiska metalliseringen kan vara av en Cr-Cu-struktur (3 um tjock, applicerad genom sprutavsättningsteknik) - Cu (3 um tjock, elektropläterad) - Ni (0,5 um tjock, elektropläterad) - Au (3 um tjock, 0:\users\EWR\DOK\WORD-DOK\p33587-b.doc 1:11» 10 15 20 25 30 522 105 3 elektropläterad). Kortet 1 har ett antal urtagningar 3, var och en exempelvis 0,6 x 0,6 x 0,16 mm med en lutnings-vinkel ot för väggarna mot pletnet för kcrtytz-in lika ct = l20°.
I detta fall, varvid skiktet av ett bindemedel 4 på botten av urtagningen är 10 um tjockt, är ett avstånd mellan ett chips 5 och urtagningens 3 övre kant lika med 87 um. Ett vidhäftningsmedel av typen aHa-C (Standard Speciñcations 'BIYO 0.028.052 TY) kan användas såsom bindemedel 4.
Chipset 5 för chipstransistom 31'I325A-5 av 0,5 x 0,5 x 0,15 mm är monterat i urtagningen 3, sä att dess yta sammanfaller med ytplanet hos kortet 1. Kontaktplattor 6 hos chipset 5 är elektriskt anslutna till det topologiska metalliseringsmönstret 2 medelst en guldtråd 7, som har en diameter av 15 um.
Urtagningen 3 (ñg. 3) kan vara metallbelagd och strukturen fór metallisering 8 kan vara exempelvis Pd-Ni (0,2 um tjock, kemiskt avsatt) - Cu (3 um, elektropläterad) - Ni (0,5 um, elektropläterad) -Au (3 um, elektropläterad).
I botten av urtagningen 3 (fig. 4) är metalliserade häl 9 åstadkomna, vilka har en diameter av exempelvis 100 um och är fyllda med ett elektriskt ledande och värmeledande material 10, exempelvis åstadkommet med koppar, preliminärt aktiverat med PdCl2+SnCl,.
Kortets l baksida är försedd med en skärmjordningsmetallisering 11 med en struktur, som är likadan som den hos metalliseringen 2, på framsidan av kortet l.
Den integrerade mikroväghybridkretsen enligt uppfinningen fungerar på följande sätt.
En signal tillförs till ingången hos transistortörstärkarsteget, vilken signal undergär en lämplig omvandling, varefter den förstärkta signalen anländer till stegets utgång.
Den nya mikrovåghybridkretsen gör det möjligt att öka reproducerbarheten hos elektriska kretsparametrar genom att minska variationen i längden hos hopkopplingstrådama (ledama) hos halvledarchipset för att öka producerbarheten beroende på en noggrannare inpassning av chipset i urtagningen samt dess orientering däri, samt beroende på en enklare anslutning mellan urtagningsmetalliseringen och det topologiska metalliseringsmönstret. Allt det ovan nämnda gör det möjligt att minska mödan med kretstrimningsproceduren.
Vidare gör metalliseringen av urtagningarna samt deras anslutning till det topologiska metalliseringsmönstret det möjligt att öka kretstillförlitligheten.
Vid beskrivning av de visade utföringsformerna av föreliggande uppfinning används för tydlighetens skull specifik snâv terminologi. Uppfinningen är emellertid inte 0:\usc|s\EWR\DOK\WORD-DOK\p33587-b.doc »- msn» 10 105 4 522 begränsad till de sålunda valda specifika termerna och det torde inses att varje sådan term täcker alla rnctsvarande element, som fisngerar på saraaa sät: och som används för att lösa samma problem. Även om föreliggande uppfmning här har beskrivits med hänvisning till den fördelaktiga uttöringsfonnen så torde inses att olika modifikationer och förändringar kan förekomma beträffande konstruktionsdetaljerna utan att man går utanför uppfinningens ram, såsom lätt torde inses av fackmannen inom området.
Alla dessa modifikationer och förändringar skall anses ligga inom gränserna för uppfmningens idé och omfattning och inom gränserna för de följande patentkraven.
Industriell fiuämpbarner Föreliggande uppfinning kan användas i halvledarmikroelektronik.
O:\users\EWR\DOK\WORD-DOK\p33587-b.doc

Claims (2)

1. 0 15 u n' n nu u n n. 1 o H " ,"_ f" - s n u .n v u v ' ' s .ur o v -----.: z: .. . - n. .n s . s . . - e - n 1 t, ~ . a x , . , | ao so u. n. IG 5 Patentkrav l. Integrerad mikrovåghybridkrets, innefattande: ett dielektriskt kort (1) med ett plan, en yta och åtminstone en urtagning (3), varvid urtagningen innefattar en vägg som lutar mot kortets plan med en vinkel (ot) av 90,1 -150°, och varvid urtagningen (3) innefattar en kontaktplatta (6); ett topologiskt metalliseringsmönster (2) på kortet (1), varvid det topologiska metalliseringsmönstret (2) är elektriskt anslutet mot kontaktplattan (6) i urtagningen; och ett halvledarchips (5) med en yta, varvid halvledarchipset är flxerat i urtagningen (3) med ett bindemedel (4), och varvid chipsets (5) yta är försedd med en kontaktplatta (6), som är i samma plan som kortets (1) yta och är elektriskt anslutet till det topologiska metalliseringsmönstret (2).
2. Integrerad mikrovåghybridkrets enligt kravet l, varvid det dielekníska kortet (1) innefattar en baksida med en skärmjordningsmetallisering (l l) och urtagningen (3) innefattar en botten med däri anordnade metalliserade hål (9), varvid de metalliserade hålen är fyllda med ett elektriskt ledande och värrneledande material (10). O:\Patent\CHF\Christer\Patent\Svaromàl\Samsung\103358700SE\p33587-b(arnended).doc
SE9801988A 1996-10-10 1998-06-04 Integrerad mikrovåghybridkrets SE522105C2 (sv)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/RU1996/000294 WO1998015981A1 (fr) 1996-10-10 1996-10-10 Circuit integre hybride et a frequence micro-ondes

Publications (3)

Publication Number Publication Date
SE9801988L SE9801988L (sv) 1998-06-04
SE9801988D0 SE9801988D0 (sv) 1998-06-04
SE522105C2 true SE522105C2 (sv) 2004-01-13

Family

ID=20130049

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9801988A SE522105C2 (sv) 1996-10-10 1998-06-04 Integrerad mikrovåghybridkrets

Country Status (5)

Country Link
US (1) US6204555B1 (sv)
JP (1) JP2000516044A (sv)
KR (1) KR19990072029A (sv)
SE (1) SE522105C2 (sv)
WO (1) WO1998015981A1 (sv)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6259148B1 (en) * 1998-08-13 2001-07-10 International Business Machines Corporation Modular high frequency integrated circuit structure
EP1258370B1 (en) * 2000-02-22 2008-12-24 Toray Engineering Co., Ltd. Noncontact id card and method of manufacturing the same
CN1421019A (zh) * 2000-04-04 2003-05-28 东丽工程株式会社 Cof组件的制造方法
DE10122221A1 (de) * 2001-05-08 2002-11-21 Danfoss Silicon Power Gmbh Leistungselektronikmodul mit einer Bodenplatte und darauf gelötetem Substrat
US6707150B1 (en) * 2002-10-24 2004-03-16 Galaxy Pcb Co., Ltd. Package support member with high heat-removing ability
JP3844467B2 (ja) * 2003-01-08 2006-11-15 沖電気工業株式会社 半導体装置及びその製造方法
US7253735B2 (en) 2003-03-24 2007-08-07 Alien Technology Corporation RFID tags and processes for producing RFID tags
JP2004361308A (ja) * 2003-06-06 2004-12-24 Fuji Electric Device Technology Co Ltd 物理量検出装置および物理量検出手段格納ケース
DE102004016940B4 (de) * 2004-04-06 2019-08-08 Continental Automotive Gmbh Schaltungsträger für einen Halbleiterchip und ein Bauelement mit einem Halbleiterchip
US7688206B2 (en) 2004-11-22 2010-03-30 Alien Technology Corporation Radio frequency identification (RFID) tag for an item having a conductive layer included or attached
US9704809B2 (en) * 2013-03-05 2017-07-11 Maxim Integrated Products, Inc. Fan-out and heterogeneous packaging of electronic components
CN105140189B (zh) * 2015-07-08 2019-04-26 华进半导体封装先导技术研发中心有限公司 板级扇出型芯片封装器件及其制备方法
CN113359248B (zh) * 2021-06-02 2022-11-15 青岛海信宽带多媒体技术有限公司 一种光模块

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52127177A (en) * 1976-04-19 1977-10-25 Toshiba Corp Semiconductor device
JPS59182545A (ja) * 1983-03-31 1984-10-17 Nec Home Electronics Ltd 混成集積回路
JPS63271944A (ja) * 1987-04-28 1988-11-09 Sumitomo Electric Ind Ltd 半導体装置
JP3190057B2 (ja) * 1990-07-02 2001-07-16 株式会社東芝 複合集積回路装置
RU2025822C1 (ru) * 1991-03-19 1994-12-30 Государственное научно-производственное предприятие "Исток" Гибридная интегральная схема
RU2004036C1 (ru) * 1991-04-25 1993-11-30 Виктор Анатольевич Иовдальский Гибридна интегральна СВЧ- и КВЧ-схема
DE4222474A1 (de) * 1992-07-09 1994-01-13 Bosch Gmbh Robert Montageeinheit für Mehrlagenhybrid mit Leistungsbauelementen
JPH06132417A (ja) * 1992-10-20 1994-05-13 Fujitsu Ltd 超高周波装置
JPH0810739B2 (ja) * 1993-02-08 1996-01-31 日本電気株式会社 ハイブリッドｉｃ
JP3292798B2 (ja) * 1995-10-04 2002-06-17 三菱電機株式会社 半導体装置

Also Published As

Publication number Publication date
SE9801988L (sv) 1998-06-04
WO1998015981A1 (fr) 1998-04-16
JP2000516044A (ja) 2000-11-28
US6204555B1 (en) 2001-03-20
SE9801988D0 (sv) 1998-06-04
KR19990072029A (ko) 1999-09-27

Similar Documents

Publication Publication Date Title
US5237204A (en) Electric potential distribution device and an electronic component case incorporating such a device
EP0236493B1 (en) Microelectronic package
US4417266A (en) Power and ground plane structure for chip carrier
CA1201820A (en) Semiconductor integrated circuit including a lead frame chip support
SE522105C2 (sv) Integrerad mikrovåghybridkrets
US5331514A (en) Integrated-circuit package
US5475264A (en) Arrangement having multilevel wiring structure used for electronic component module
US6005778A (en) Chip stacking and capacitor mounting arrangement including spacers
US5673478A (en) Method of forming an electronic device having I/O reroute
US5311058A (en) Integrated circuit power distribution system
JPH01132151A (ja) 集積回路を相互接続するためのモジユ−ル
EP1492220A3 (en) IGBT-module
US6081030A (en) Semiconductor device having separated exchange means
SE522106C2 (sv) Integrerad mikrovåghybridkrets
US7288846B2 (en) Semiconductor chip having pads with plural junctions for different assembly methods
EP0145862A2 (en) Metallization of a ceramic substrate
EP0357758A1 (en) HERMETIC PACKING FOR INTEGRATED CIRCUIT CHIPS.
JPS60161641A (ja) 回路パツケージとその製造方法
GB1376939A (en) Integrated circuit mounting and connection systems
GB1152809A (en) Electric Circuit Assembly
US4631572A (en) Multiple path signal distribution to large scale integration chips
US10978374B2 (en) Semiconductor package for discharging heat generated by semiconductor chip
US5898128A (en) Electronic component
US6288345B1 (en) Compact z-axis DC and control signals routing substrate
EP0262493B1 (en) Electronic package with distributed decoupling capacitors

Legal Events

Date Code Title Description
NUG Patent has lapsed