JP2000516044A - マイクロ波ハイブリッド集積回路 - Google Patents

マイクロ波ハイブリッド集積回路

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JP2000516044A
JP2000516044A JP51743398A JP51743398A JP2000516044A JP 2000516044 A JP2000516044 A JP 2000516044A JP 51743398 A JP51743398 A JP 51743398A JP 51743398 A JP51743398 A JP 51743398A JP 2000516044 A JP2000516044 A JP 2000516044A
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substrate
chip
integrated circuit
hybrid integrated
microwave hybrid
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イオフダルスキー,ビクトル・アナトーリエビッチ
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サムソン・エレクトロニクス・カンパニー・リミテッド
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Abstract

(57)【要約】 マイクロ波ハイブリッド集積回路は、トポロジー的な金属被覆パターン(2)とたくさんのくぼみ(3)とを備える誘電体基板(1)を備え、半導体チップ(5)はバインダー(4)によって取付ける。接触パッド(6)を備えるチップ(5)のおもて面は、基板(1)の表面と同一平面上にあり、チップ(5)の接触パッド(6)は、トポロジー的な金属被覆パターン(2)と電気的に接続する。くぼみ(3)の壁は、基板(1)面に対して90.1°〜150°の角度(α)で傾いている。

Description

【発明の詳細な説明】 マイクロ波ハイブリッド集積回路技術分野 本発明は、一般に、電子工学に関し、特に、マイクロ波ハイブリッド集積回路 (IC)に関する。背景技術 以下のマイクロ波ハイブリッドICが知られている。すなわち、その回路は、 トポロジー的な金属被覆パターンと、半導体チップとを有する誘電体基板を備え 、半導体チップを基板中に配置した結果、接触パッドを備える各チップのおもて 面が基板表面と同じ面に位置しており、チップの接触パッドは、トポロジー的な 金属被覆パターンと電気的に接続している。(US,A,4,722,914) しかしながら、前記ハイブリッドICは、壁の一方から他方へくぼみの底に沿 って半導体チップが移動可能であることによって、相互連結ワイヤーの長さが変 化すると、回路電気パラメータのばらつきを有する。 別の従来技術マイクロ波ハイブリッドICが知られている。すなわち、その回 路は、トポロジー的な金属被覆パターンとくぼみを有する誘電体基板を備え、チ ップタイプの半導体デバイスのチップはバインダーによって固定されており、接 触パッドを有するチップのおもて面は、基板表面と同一平面上にあり、チップの 接触パッドは、トポロジー的な金属被覆パターンと電気的に接続している。(J P,B,49−12794) 前記のハイブリッドICは、ワイヤーを相互連結する長さが異なって取付ける 間に、くぼみの底に沿ってチップが移動するために、その電気パラメータの再現 性が悪い。発明の概要 本発明の主たる目的は、マイクロ波ハイブリッド集積回路を提供することであ る。すなわち、くぼみを誘電体基板中に形成し、半導体チップをくぼみに取付け 、その結果、ICの電気パラメータの再現性と製造性とが良くなる。 前述の目的は以下のことによって達成される。マイクロ波ハイブリッドICに おいて、本発明によって、トポロジー的な金属被覆パターンとたくさんのくぼみ を備えた誘電体基板とを備え、半導体チップをバインダーによって取付け、接触 パッドを備えたチップのおもて面は、基板表面と同一平面上にあるが、チップの 接触パッドがトポロジー的な金属被覆パターンと電気的に接続しており、各くぼ みの壁は、基板表面に対して90.1°〜150°の角度で傾いている。 90.1°より小さい基板表面に対する壁傾斜角度を形成することは、ポジテ ィブな結果を与えない。150°より大きい前記角度を形成することは、実質的 に接続リード線の長さを長くし、それゆえに、擬似インダクタンスを大きくする 。 くぼみを金属被覆した金属コーティングは、基板のトポロジー的な金属被覆と 電気的に接続する。基板は、その裏面にシールド接地金属被覆を備え、くぼみの 底に金属被覆した穴が形成され、シールド接地金属被覆との接続のために導電性 及び熱伝導性の材料で満たす。 くぼみの壁を基板表面に対してα=90.1°〜150°の角度で傾けること によって、以下のことが確実になる。 第1に、チップがくぼみの底に沿って移動する可能性が小さくなり、トポロジ ー的な金属被覆と接触パッドとを相互連結する導体長の変化が小さくなって、そ の結果、回路電気パラメータの再現性が高くなる。 第2に、くぼみ金属被覆とトポロジー的な金属被覆との間の電気接続が簡単に なるのと同様に、くぼみへのチップの取付け精度と、その位置決め精度が高くな り、それによって製造しやすくなる。図面の簡単な説明 本発明は、いくつかの代表的な実施形態について添付の図面を参照して説明す る。 図1は、本願のマイクロ波ハイブリッドICの断面図である。 図2は、図1の平面図である。 図3は、本願のマイクロ波ハイブリッドICの別の実施形態の断面図である。 図4は、本願のマイクロ波ハイブリッドICのさらに別の実施形態の断面図で ある。詳細な説明 本発明によるマイクロ波ハイブリッドICは、例えば、ポリコールからなる、 厚さ0.5mmの誘電体基板1(図1と図2)を備え、そのおもて面にトポロジ ー的な金属被覆パターン2を有する。トポロジー的な金属被覆は、Cr−Cu( スプレー付着技術によって厚さ3μmを形成)−Cu(電気メッキによって厚さ 3μmを形成)−Ni(電気メッキによって厚さ0.5μmを形成)−Au(電 気メッキによって厚さ3μmを形成)という構造である。基板1がたくさんのく ぼみ3を有し、そのそれぞれは、例えば、0.6mm×0.6mm×0.16m mであり、基板表面に対してα=120°の壁傾斜角度αを有する。この場合、 くぼみの底のバインダー4の層は厚さ10μmであり、チップ5とくぼみ3の上 部エッジとの距離は87μmである。タイプ エ.チェ.エ−エス(ЭЧЭ−С)( 標準仕様書 ウィ.ウ.オ(ЫУО)0.028.052 テ.ウ(ТУ))の接 着剤が、バインダー4として用いられる。 0.5mm×0.5mm×0.15mmのチップトランジスタ3ペー325ア ー−5(3Π325A−5)のチップ5は、くぼみ3に取付け、その表面が基板 1の表面と一致している。チップ5の接触パッド6は、直径15μmの金ワイヤ ー7によってトポロジー的な金属被覆パターン2と電気的に接続している。 くぼみ3(図3)は、金属コートしており、金属被覆8の構造は、例えば、P d−Ni(厚さ0.2μmを化学的に形成)−Cu(厚さ3μmを電気メッキに よって形成)−Ni(厚さ0.5μmを電気メッキによって形成)−Au(厚さ 3μmを電気メッキによって形成)である。 くぼみ3(図4)の底において、金属被覆した穴9は、例えば、直径100μ mを有し、導電性及び熱伝導性の材料10、たとえば、予備的に活性化した銅に PdCl2+SnCl2で成長させた材料で満たして作成する。基板1の裏面は、 基板1のおもて面に金属被覆2の構造と似た構造のシールド接地金属被覆11を 備える。 本発明によるマイクロ波ハイブリッド集積回路は、次のように作用する。 トランジスタ増幅器ステージの入力に加えた信号は、適切に変換され、その後 、 増幅信号がステージ出力に達する。 本願のマイクロ波ハイブリッド集積回路により、半導体チップの相互連結ワイ ヤー(リード)長さの変化が減り、したがって、電気回路パラメータが再現しや すくなる。そして、くぼみ金属被覆とトポロジー的な金属被覆パターンとの間の 単純な接続と同様に、くぼみへのチップの正確な取付けと位置決めによって製造 しやすくなる。上述のすべてによって、回路トリミング手順の困難さが低減する 。 さらに、くぼみの金属被覆とトポロジー的な金属被覆パターンへのそれらの接 続は、回路の信頼性が高くなる。 本発明の開示した実施形態の記載において、明確にするために、具体的な狭い 意味の用語を用いている。しかしながら、本発明は、選択した具体的な用語に制 限されない。そのような各用語が、類似した方法で作用し、類似した問題を解決 するために用いる、全ての等価なエレメントをカバーすることは、理解されるで あろう。 本発明は、本明細書において、好ましい実施形態を記載しているけれども、当 業者によって容易に理解されるように、本発明の精神と範囲から逸脱することな く構造の詳細にいろいろな変形を加えることは、理解される。 これらの変形した実施形態の全てが、本発明と請求項の精神及び請求の範囲内 にあることを考慮するべきである。

Claims (1)

  1. 【特許請求の範囲】 1.トポロジー的な金属被覆パターン(2)と多くのくぼみ(3)とを備えた誘 電体基板(1)を備え、半導体チップ(5)はバインダー(4)によって取付け られ、接触パッド(6)を備えるチップ(5)表面は基板(1)の表面と同一平 面上にあるが、チップ(5)の接触パッド(6)はトポロジー的な金属被覆パタ ーン(2)と電気的に接続しているマイクロ波ハイブリッド集積回路において、 各くぼみ(3)の壁が、基板(1)面に対して90.1°〜150°の角度( α)で傾いていることを特徴とするマイクロ波ハイブリッド集積回路。 2.くぼみ(3)を金属被覆して、くぼみ(3)の金属被覆(8)は基板(1) の金属被覆のトポロジー的なパターン(2)と電気的に接続していることを特徴 とする請求項1記載のマイクロ波ハイブリッド集積回路。 3.基板(1)は、シールド接地金属被覆(11)をその裏面に有し、金属被覆 した穴(9)はくぼみ(3)の底に備え、前記穴が導電性及び熱伝導性の材料( 10)で満たされていることを特徴とする請求項1又は請求項2記載のマイクロ 波ハイブリッド集積回路。
JP51743398A 1996-10-10 1996-10-10 マイクロ波ハイブリッド集積回路 Pending JP2000516044A (ja)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004214543A (ja) * 2003-01-08 2004-07-29 Oki Electric Ind Co Ltd 半導体装置及びその製造方法

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6259148B1 (en) * 1998-08-13 2001-07-10 International Business Machines Corporation Modular high frequency integrated circuit structure
DE60137117D1 (de) * 2000-02-22 2009-02-05 Toray Eng Co Ltd Kontaktlose ic-karte und verfahren zu ihrer herstellung
WO2001075789A1 (fr) * 2000-04-04 2001-10-11 Toray Engineering Company, Limited Procede de production de boitier cof
DE10122221A1 (de) * 2001-05-08 2002-11-21 Danfoss Silicon Power Gmbh Leistungselektronikmodul mit einer Bodenplatte und darauf gelötetem Substrat
US6707150B1 (en) * 2002-10-24 2004-03-16 Galaxy Pcb Co., Ltd. Package support member with high heat-removing ability
US7253735B2 (en) 2003-03-24 2007-08-07 Alien Technology Corporation RFID tags and processes for producing RFID tags
JP2004361308A (ja) * 2003-06-06 2004-12-24 Fuji Electric Device Technology Co Ltd 物理量検出装置および物理量検出手段格納ケース
DE102004016940B4 (de) * 2004-04-06 2019-08-08 Continental Automotive Gmbh Schaltungsträger für einen Halbleiterchip und ein Bauelement mit einem Halbleiterchip
US7688206B2 (en) 2004-11-22 2010-03-30 Alien Technology Corporation Radio frequency identification (RFID) tag for an item having a conductive layer included or attached
US9704809B2 (en) * 2013-03-05 2017-07-11 Maxim Integrated Products, Inc. Fan-out and heterogeneous packaging of electronic components
CN105140189B (zh) * 2015-07-08 2019-04-26 华进半导体封装先导技术研发中心有限公司 板级扇出型芯片封装器件及其制备方法
CN113359248B (zh) * 2021-06-02 2022-11-15 青岛海信宽带多媒体技术有限公司 一种光模块

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52127177A (en) * 1976-04-19 1977-10-25 Toshiba Corp Semiconductor device
JPS59182545A (ja) * 1983-03-31 1984-10-17 Nec Home Electronics Ltd 混成集積回路
JPH04218953A (ja) * 1990-07-02 1992-08-10 Toshiba Corp 複合集積回路装置
JPH06132417A (ja) * 1992-10-20 1994-05-13 Fujitsu Ltd 超高周波装置
JPH06232287A (ja) * 1993-02-08 1994-08-19 Nec Corp ハイブリッドic
JPH07508858A (ja) * 1992-07-09 1995-09-28 ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング 電力素子を備えた多層ハイブリッド用の組立ユニット

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63271944A (ja) * 1987-04-28 1988-11-09 Sumitomo Electric Ind Ltd 半導体装置
RU2025822C1 (ru) * 1991-03-19 1994-12-30 Государственное научно-производственное предприятие "Исток" Гибридная интегральная схема
RU2004036C1 (ru) * 1991-04-25 1993-11-30 Виктор Анатольевич Иовдальский Гибридна интегральна СВЧ- и КВЧ-схема
JP3292798B2 (ja) * 1995-10-04 2002-06-17 三菱電機株式会社 半導体装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52127177A (en) * 1976-04-19 1977-10-25 Toshiba Corp Semiconductor device
JPS59182545A (ja) * 1983-03-31 1984-10-17 Nec Home Electronics Ltd 混成集積回路
JPH04218953A (ja) * 1990-07-02 1992-08-10 Toshiba Corp 複合集積回路装置
JPH07508858A (ja) * 1992-07-09 1995-09-28 ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング 電力素子を備えた多層ハイブリッド用の組立ユニット
JPH06132417A (ja) * 1992-10-20 1994-05-13 Fujitsu Ltd 超高周波装置
JPH06232287A (ja) * 1993-02-08 1994-08-19 Nec Corp ハイブリッドic

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004214543A (ja) * 2003-01-08 2004-07-29 Oki Electric Ind Co Ltd 半導体装置及びその製造方法
US7151320B2 (en) 2003-01-08 2006-12-19 Oki Electric Industry Co., Ltd. Semiconductor device with improved design freedom of external terminal
US7736944B2 (en) 2003-01-08 2010-06-15 Oki Semiconductor Co., Ltd. Semiconductor device with improved design freedom of external terminal

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SE9801988D0 (sv) 1998-06-04

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