KR102083688B1 - Ｓｏｉ 웨이퍼를 인시츄로 패시베이션하기 위한 방법 - Google Patents

Ｓｏｉ 웨이퍼를 인시츄로 패시베이션하기 위한 방법 Download PDF

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KR102083688B1
KR102083688B1 KR1020137002599A KR20137002599A KR102083688B1 KR 102083688 B1 KR102083688 B1 KR 102083688B1 KR 1020137002599 A KR1020137002599 A KR 1020137002599A KR 20137002599 A KR20137002599 A KR 20137002599A KR 102083688 B1 KR102083688 B1 KR 102083688B1
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wafer
chamber
cleaved
cleaved surface
soi wafer
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KR20130129897A (ko
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마이클 제이. 리스
데일 에이. 위틀
안카 스테파네스쿠
앤드류 엠. 존스
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글로벌웨이퍼스 씨오., 엘티디.
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/7806—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
KR1020137002599A 2010-06-30 2011-06-30 Ｓｏｉ 웨이퍼를 인시츄로 패시베이션하기 위한 방법 Active KR102083688B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US35999810P 2010-06-30 2010-06-30
US61/359,998 2010-06-30
PCT/IB2011/052903 WO2012001659A2 (en) 2010-06-30 2011-06-30 Methods for in-situ passivation of silicon-on-insulator wafers

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KR1020187009456A Division KR20180037326A (ko) 2010-06-30 2011-06-30 Ｓｏｉ 웨이퍼를 인시츄로 패시베이션하기 위한 방법

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KR20130129897A KR20130129897A (ko) 2013-11-29
KR102083688B1 true KR102083688B1 (ko) 2020-03-02

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KR1020187009456A Ceased KR20180037326A (ko) 2010-06-30 2011-06-30 Ｓｏｉ 웨이퍼를 인시츄로 패시베이션하기 위한 방법
KR1020137002599A Active KR102083688B1 (ko) 2010-06-30 2011-06-30 Ｓｏｉ 웨이퍼를 인시츄로 패시베이션하기 위한 방법
KR1020197020821A Ceased KR20190087668A (ko) 2010-06-30 2011-06-30 Ｓｏｉ 웨이퍼를 인시츄로 패시베이션하기 위한 방법

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Country Link
US (1) US8859393B2 (enExample)
EP (1) EP2589075A2 (enExample)
JP (1) JP5989642B2 (enExample)
KR (3) KR20180037326A (enExample)
CN (1) CN102959697A (enExample)
SG (1) SG186853A1 (enExample)
TW (1) TW201216414A (enExample)
WO (1) WO2012001659A2 (enExample)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102427097B (zh) * 2011-11-23 2014-05-07 中国科学院物理研究所 一种硅的氧化钝化方法及钝化装置
US8747598B2 (en) 2012-04-25 2014-06-10 Gtat Corporation Method of forming a permanently supported lamina
WO2015112308A1 (en) 2014-01-23 2015-07-30 Sunedison Semiconductor Limited High resistivity soi wafers and a method of manufacturing thereof
US9899499B2 (en) 2014-09-04 2018-02-20 Sunedison Semiconductor Limited (Uen201334164H) High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss
US9853133B2 (en) * 2014-09-04 2017-12-26 Sunedison Semiconductor Limited (Uen201334164H) Method of manufacturing high resistivity silicon-on-insulator substrate
US10224233B2 (en) 2014-11-18 2019-03-05 Globalwafers Co., Ltd. High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed by He-N2 co-implantation
US10483152B2 (en) 2014-11-18 2019-11-19 Globalwafers Co., Ltd. High resistivity semiconductor-on-insulator wafer and a method of manufacturing
EP3221884B1 (en) 2014-11-18 2022-06-01 GlobalWafers Co., Ltd. High resistivity semiconductor-on-insulator wafers with charge trapping layers and method of manufacturing thereof
EP4120320A1 (en) 2015-03-03 2023-01-18 GlobalWafers Co., Ltd. Charge trapping polycrystalline silicon films on silicon substrates with controllable film stress
US9881832B2 (en) 2015-03-17 2018-01-30 Sunedison Semiconductor Limited (Uen201334164H) Handle substrate for use in manufacture of semiconductor-on-insulator structure and method of manufacturing thereof
CN107408532A (zh) 2015-03-17 2017-11-28 太阳能爱迪生半导体有限公司 用于绝缘体上半导体结构的制造的热稳定电荷捕获层
US10332782B2 (en) 2015-06-01 2019-06-25 Globalwafers Co., Ltd. Method of manufacturing silicon germanium-on-insulator
US10304722B2 (en) 2015-06-01 2019-05-28 Globalwafers Co., Ltd. Method of manufacturing semiconductor-on-insulator
CN117198983A (zh) 2015-11-20 2023-12-08 环球晶圆股份有限公司 使半导体表面平整的制造方法
US9831115B2 (en) 2016-02-19 2017-11-28 Sunedison Semiconductor Limited (Uen201334164H) Process flow for manufacturing semiconductor on insulator structures in parallel
US10468294B2 (en) 2016-02-19 2019-11-05 Globalwafers Co., Ltd. High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed on a substrate with a rough surface
WO2017142849A1 (en) 2016-02-19 2017-08-24 Sunedison Semiconductor Limited Semiconductor on insulator structure comprising a buried high resistivity layer
WO2017155804A1 (en) 2016-03-07 2017-09-14 Sunedison Semiconductor Limited Method of manufacturing a semiconductor on insulator structure by a pressurized bond treatment
WO2017155808A1 (en) 2016-03-07 2017-09-14 Sunedison Semiconductor Limited Semiconductor on insulator structure comprising a plasma nitride layer and method of manufacture thereof
EP3758050A1 (en) 2016-03-07 2020-12-30 GlobalWafers Co., Ltd. Semiconductor on insulator structure comprising a low temperature flowable oxide layer and method of manufacture thereof
WO2017155806A1 (en) 2016-03-07 2017-09-14 Sunedison Semiconductor Limited Semiconductor on insulator structure comprising a plasma oxide layer and method of manufacture thereof
WO2017214084A1 (en) 2016-06-08 2017-12-14 Sunedison Semiconductor Limited High resistivity single crystal silicon ingot and wafer having improved mechanical strength
US10269617B2 (en) 2016-06-22 2019-04-23 Globalwafers Co., Ltd. High resistivity silicon-on-insulator substrate comprising an isolation region
SG11201903090SA (en) 2016-10-26 2019-05-30 Globalwafers Co Ltd High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiency
JP6801105B2 (ja) 2016-12-05 2020-12-16 グローバルウェーハズ カンパニー リミテッドＧｌｏｂａｌＷａｆｅｒｓ Ｃｏ．，Ｌｔｄ． 高抵抗シリコンオンインシュレータ構造及びその製造方法
SG10201913071XA (en) 2016-12-28 2020-03-30 Sunedison Semiconductor Ltd Method of treating silicon wafers to have intrinsic gettering and gate oxide integrity yield
FR3061988B1 (fr) 2017-01-13 2019-11-01 Soitec Procede de lissage de surface d'un substrat semiconducteur sur isolant
JP7034186B2 (ja) 2017-07-14 2022-03-11 サンエディソン・セミコンダクター・リミテッド 絶縁体上半導体構造の製造方法
US10916416B2 (en) 2017-11-14 2021-02-09 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor wafer with modified surface and fabrication method thereof
JP7160943B2 (ja) 2018-04-27 2022-10-25 グローバルウェーハズ カンパニー リミテッド 半導体ドナー基板からの層移転を容易にする光アシスト板状体形成
JP7123182B2 (ja) 2018-06-08 2022-08-22 グローバルウェーハズ カンパニー リミテッド シリコン箔層の移転方法
US11296277B2 (en) 2018-10-16 2022-04-05 Samsung Electronics Co., Ltd. Variable resistance memory device having an anti-oxidation layer and a method of manufacturing the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3836786A (en) * 1967-01-04 1974-09-17 Purification Sciences Inc Dielectric liquid-immersed corona generator
JP2000294754A (ja) 1999-04-07 2000-10-20 Denso Corp 半導体基板及び半導体基板の製造方法並びに半導体基板製造装置
US20040077184A1 (en) 2002-10-17 2004-04-22 Applied Materials, Inc. Apparatuses and methods for depositing an oxide film

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1030102A (en) * 1972-08-17 1978-04-25 Purification Sciences Inc. Dielectric liquid-immersed corona generator
US5000113A (en) * 1986-12-19 1991-03-19 Applied Materials, Inc. Thermal CVD/PECVD reactor and use for thermal chemical vapor deposition of silicon dioxide and in-situ multi-step planarized process
JPH07118522B2 (ja) * 1990-10-24 1995-12-18 インターナショナル・ビジネス・マシーンズ・コーポレイション 基板表面を酸化処理するための方法及び半導体の構造
JPH05259153A (ja) * 1992-03-12 1993-10-08 Fujitsu Ltd シリコン酸化膜の製造方法と製造装置
JPH0766195A (ja) * 1993-06-29 1995-03-10 Sumitomo Sitix Corp シリコンウェーハの表面酸化膜形成方法
CN1104264A (zh) * 1994-09-02 1995-06-28 复旦大学 热壁密装低温低压淀积二氧化硅薄膜技术
US5880029A (en) * 1996-12-27 1999-03-09 Motorola, Inc. Method of passivating semiconductor devices and the passivated devices
US5972802A (en) * 1997-10-07 1999-10-26 Seh America, Inc. Prevention of edge stain in silicon wafers by ozone dipping
JP3153162B2 (ja) * 1997-10-08 2001-04-03 松下電子工業株式会社 シリコン酸化膜の形成方法
US20020175143A1 (en) * 2001-05-22 2002-11-28 Seh America, Inc. Processes for polishing wafers
JP4614416B2 (ja) 2003-05-29 2011-01-19 日東電工株式会社 半導体チップの製造方法およびダイシング用シート貼付け装置
JP2007149723A (ja) 2005-11-24 2007-06-14 Sumco Corp 貼り合わせウェーハの製造方法
US7939424B2 (en) * 2007-09-21 2011-05-10 Varian Semiconductor Equipment Associates, Inc. Wafer bonding activated by ion implantation
SG161151A1 (en) 2008-10-22 2010-05-27 Semiconductor Energy Lab Soi substrate and method for manufacturing the same
EP2368264A1 (en) 2008-11-26 2011-09-28 MEMC Electronic Materials, Inc. Method for processing a silicon-on-insulator structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3836786A (en) * 1967-01-04 1974-09-17 Purification Sciences Inc Dielectric liquid-immersed corona generator
JP2000294754A (ja) 1999-04-07 2000-10-20 Denso Corp 半導体基板及び半導体基板の製造方法並びに半導体基板製造装置
US20040077184A1 (en) 2002-10-17 2004-04-22 Applied Materials, Inc. Apparatuses and methods for depositing an oxide film

Also Published As

Publication number Publication date
CN102959697A (zh) 2013-03-06
SG186853A1 (en) 2013-02-28
US20120003814A1 (en) 2012-01-05
KR20130129897A (ko) 2013-11-29
EP2589075A2 (en) 2013-05-08
KR20180037326A (ko) 2018-04-11
WO2012001659A3 (en) 2012-03-01
KR20190087668A (ko) 2019-07-24
TW201216414A (en) 2012-04-16
JP2013534731A (ja) 2013-09-05
WO2012001659A2 (en) 2012-01-05
JP5989642B2 (ja) 2016-09-07
US8859393B2 (en) 2014-10-14

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