KR101762242B1 - 정보처리장치, 정보처리장치의 제어방법 및 제어 프로그램을 기억하는 비일시 컴퓨터 판독가능한 기억매체 - Google Patents

정보처리장치, 정보처리장치의 제어방법 및 제어 프로그램을 기억하는 비일시 컴퓨터 판독가능한 기억매체 Download PDF

Info

Publication number
KR101762242B1
KR101762242B1 KR1020140125697A KR20140125697A KR101762242B1 KR 101762242 B1 KR101762242 B1 KR 101762242B1 KR 1020140125697 A KR1020140125697 A KR 1020140125697A KR 20140125697 A KR20140125697 A KR 20140125697A KR 101762242 B1 KR101762242 B1 KR 101762242B1
Authority
KR
South Korea
Prior art keywords
memory
volatile memory
detected
setting
cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020140125697A
Other languages
English (en)
Korean (ko)
Other versions
KR20150034096A (ko
Inventor
요시히사 노무라
Original Assignee
캐논 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 캐논 가부시끼가이샤 filed Critical 캐논 가부시끼가이샤
Publication of KR20150034096A publication Critical patent/KR20150034096A/ko
Application granted granted Critical
Publication of KR101762242B1 publication Critical patent/KR101762242B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3051—Monitoring arrangements for monitoring the configuration of the computing system or of the computing system component, e.g. monitoring the presence of processing resources, peripherals, I/O links, software programs
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/875—Monitoring of systems including the internet
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Record Information Processing For Printing (AREA)
  • Memory System (AREA)
  • Power Sources (AREA)
  • Accessory Devices And Overall Control Thereof (AREA)
KR1020140125697A 2013-09-25 2014-09-22 정보처리장치, 정보처리장치의 제어방법 및 제어 프로그램을 기억하는 비일시 컴퓨터 판독가능한 기억매체 Active KR101762242B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2013-198330 2013-09-25
JP2013198330A JP6165008B2 (ja) 2013-09-25 2013-09-25 メモリ制御装置、メモリ制御方法、情報機器及びプログラム

Publications (2)

Publication Number Publication Date
KR20150034096A KR20150034096A (ko) 2015-04-02
KR101762242B1 true KR101762242B1 (ko) 2017-07-27

Family

ID=51655549

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020140125697A Active KR101762242B1 (ko) 2013-09-25 2014-09-22 정보처리장치, 정보처리장치의 제어방법 및 제어 프로그램을 기억하는 비일시 컴퓨터 판독가능한 기억매체

Country Status (5)

Country Link
US (1) US10268257B2 (enExample)
EP (1) EP2857979B1 (enExample)
JP (1) JP6165008B2 (enExample)
KR (1) KR101762242B1 (enExample)
CN (1) CN104464813A (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017107164A1 (zh) * 2015-12-25 2017-06-29 研祥智能科技股份有限公司 异构混合内存架构的计算机系统及其控制方法、内存检测系统
US9830086B2 (en) * 2016-03-03 2017-11-28 Samsung Electronics Co., Ltd. Hybrid memory controller for arbitrating access to volatile and non-volatile memories in a hybrid memory group
US10592114B2 (en) 2016-03-03 2020-03-17 Samsung Electronics Co., Ltd. Coordinated in-module RAS features for synchronous DDR compatible memory
US11003381B2 (en) * 2017-03-07 2021-05-11 Samsung Electronics Co., Ltd. Non-volatile memory storage device capable of self-reporting performance capabilities
US10650899B2 (en) * 2017-04-27 2020-05-12 Everspin Technologies, Inc. Delayed write-back in memory with calibration support
JP7406895B2 (ja) * 2019-10-23 2023-12-28 キヤノン株式会社 情報処理装置および情報処理装置の制御方法
CN111190540B (zh) * 2019-12-25 2021-06-04 晶晨半导体(上海)股份有限公司 内存接口写入均衡的控制方法及装置
CN117280410A (zh) * 2022-04-22 2023-12-22 京东方科技集团股份有限公司 读时序控制方法、装置及计算机可读存储介质

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012109939A (ja) * 2010-10-29 2012-06-07 Ricoh Co Ltd 画像処理装置、省電力復帰制御方法、省電力復帰制御プログラム及び記録媒体
KR101499304B1 (ko) 2010-01-29 2015-03-05 캐논 가부시끼가이샤 정보 처리 장치 및 정보 처리 장치의 제어 방법

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58125125A (ja) * 1982-01-21 1983-07-26 Toshiba Corp プログラムの起動方法
JPH04248641A (ja) * 1991-02-05 1992-09-04 Sanyo Electric Co Ltd メモリ制御装置
US5918242A (en) * 1994-03-14 1999-06-29 International Business Machines Corporation General-purpose customizable memory controller
KR0158489B1 (ko) * 1995-12-20 1998-12-15 김광호 반도체 메모리 디바이스의 구분방법
US6681286B2 (en) * 2000-01-25 2004-01-20 Via Technologies, Inc. Control chipset having dual-definition pins for reducing circuit layout of memory slot
TW493119B (en) * 2001-03-28 2002-07-01 Via Tech Inc Method for automatically identifying the type of memory and motherboard using the same
US6989861B2 (en) * 2001-09-14 2006-01-24 Hewlett-Packard Development Company, L.P. User selection of power-on configuration
US7627464B2 (en) * 2002-04-18 2009-12-01 Standard Microsystems Corporation Bootable solid state floppy disk drive
EP1408510A3 (en) * 2002-05-17 2005-05-18 Matsushita Electric Industrial Co., Ltd. Memory control apparatus, method and program
US7296171B2 (en) * 2004-11-10 2007-11-13 Microsoft Corporation Selecting a power state based on predefined parameters
US20060245230A1 (en) * 2005-04-29 2006-11-02 Ambroggi Luca D Memory module and method for operating a memory module
GB2426360A (en) * 2005-05-18 2006-11-22 Symbian Software Ltd Reorganisation of memory for conserving power in a computing device
US7321524B2 (en) * 2005-10-17 2008-01-22 Rambus Inc. Memory controller with staggered request signal output
WO2008040028A2 (en) * 2006-09-28 2008-04-03 Virident Systems, Inc. Systems, methods, and apparatus with programmable memory control for heterogeneous main memory
US7594073B2 (en) * 2006-09-29 2009-09-22 Intel Corporation Method and apparatus for caching memory content on a computing system to facilitate instant-on resuming from a hibernation state
JP2008129351A (ja) * 2006-11-21 2008-06-05 Toshiba Corp 画像表示装置及び画像表示方法
US8396515B2 (en) * 2007-11-30 2013-03-12 Symbol Technologies, Inc. Dynamic battery capacity allocation for data retention among mobile computers and electronic devices
US8738840B2 (en) * 2008-03-31 2014-05-27 Spansion Llc Operating system based DRAM/FLASH management scheme
TWI375888B (en) 2008-05-16 2012-11-01 Phison Electronics Corp Method, apparatus and controller for managing memories
US8169839B2 (en) * 2009-02-11 2012-05-01 Stec, Inc. Flash backed DRAM module including logic for isolating the DRAM
US8977831B2 (en) * 2009-02-11 2015-03-10 Stec, Inc. Flash backed DRAM module storing parameter information of the DRAM module in the flash
US8255620B2 (en) * 2009-08-11 2012-08-28 Texas Memory Systems, Inc. Secure Flash-based memory system with fast wipe feature
US9110568B2 (en) * 2009-10-13 2015-08-18 Google Inc. Browser tab management
US8694812B2 (en) * 2010-03-29 2014-04-08 Dot Hill Systems Corporation Memory calibration method and apparatus for power reduction during flash operation
JP2012033002A (ja) * 2010-07-30 2012-02-16 Toshiba Corp メモリ管理装置およびメモリ管理方法
WO2012160405A1 (en) * 2011-05-26 2012-11-29 Sony Ericsson Mobile Communications Ab Optimized hibernate mode for wireless device
JP2013004043A (ja) 2011-06-22 2013-01-07 Fuji Xerox Co Ltd 情報処理装置、画像形成装置およびプログラム
US20130046934A1 (en) * 2011-08-15 2013-02-21 Robert Nychka System caching using heterogenous memories
US9069551B2 (en) * 2011-12-22 2015-06-30 Sandisk Technologies Inc. Systems and methods of exiting hibernation in response to a triggering event
EP2620838B1 (en) * 2012-01-26 2015-04-22 ST-Ericsson SA Automatic partial array self-refresh
KR20140026889A (ko) * 2012-08-23 2014-03-06 삼성전자주식회사 선택적으로 리프레쉬를 수행하는 저항성 메모리 장치 및 저항성 메모리장치의 리프레쉬 방법
JP5787852B2 (ja) * 2012-09-07 2015-09-30 株式会社東芝 制御装置、情報処理装置、制御方法およびプログラム
KR20150098649A (ko) * 2012-12-22 2015-08-28 퀄컴 인코포레이티드 비-휘발성 메모리의 이용을 통한 휘발성 메모리의 전력 소비 감소
US9032139B2 (en) * 2012-12-28 2015-05-12 Intel Corporation Memory allocation for fast platform hibernation and resumption of computing systems
KR20140093505A (ko) * 2013-01-18 2014-07-28 삼성전자주식회사 단말기의 메모리 확장 장치 및 방법
US9286985B2 (en) * 2013-02-12 2016-03-15 Kabushiki Kaisha Toshiba Semiconductor device with power mode transitioning operation
JP6087662B2 (ja) * 2013-02-28 2017-03-01 株式会社東芝 制御装置、制御プログラム及び情報処理システム
US20140281148A1 (en) * 2013-03-15 2014-09-18 Kabushiki Kaisha Toshiba Memory system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101499304B1 (ko) 2010-01-29 2015-03-05 캐논 가부시끼가이샤 정보 처리 장치 및 정보 처리 장치의 제어 방법
JP2012109939A (ja) * 2010-10-29 2012-06-07 Ricoh Co Ltd 画像処理装置、省電力復帰制御方法、省電力復帰制御プログラム及び記録媒体

Also Published As

Publication number Publication date
JP2015064758A (ja) 2015-04-09
KR20150034096A (ko) 2015-04-02
EP2857979B1 (en) 2016-08-31
JP6165008B2 (ja) 2017-07-19
US10268257B2 (en) 2019-04-23
US20150089267A1 (en) 2015-03-26
EP2857979A1 (en) 2015-04-08
CN104464813A (zh) 2015-03-25

Similar Documents

Publication Publication Date Title
KR101762242B1 (ko) 정보처리장치, 정보처리장치의 제어방법 및 제어 프로그램을 기억하는 비일시 컴퓨터 판독가능한 기억매체
US10109328B2 (en) Memory controller for adjusting timing based on memory power states
JP2010218142A (ja) データ記憶装置、及びデータ記憶装置の制御方法
JP2011095916A (ja) 電子機器
US20160062775A1 (en) Information processing apparatus including main system and subsystem
JP4298610B2 (ja) データ記憶装置
US10754415B2 (en) Control apparatus that controls memory and control method thereof
US20150062613A1 (en) Image forming apparatus capable of preventing data leakage and control method therefor, and storage medium
US20150052341A1 (en) Information processing apparatus enabling high-speed start-up, control method therefor, and storage medium storing control program therefor
JP2009093669A (ja) 情報処理装置および情報処理方法
JP6274774B2 (ja) メモリインターフェース装置及びその制御方法
US9785221B2 (en) Power control of a plurality of functional units
US20110292448A1 (en) Program execution control method
JP5889833B2 (ja) 画像形成装置及びその起動制御方法
JP4882807B2 (ja) Ｓｄｒａｍ制御回路及び情報処理装置
JP6700739B2 (ja) コントローラおよび制御方法
US20170153688A1 (en) Control apparatus for controlling memory and control method for power saving of memory
JP2016218749A (ja) 情報処理装置、情報処理方法、及びプログラム
JP2007010970A (ja) 画像表示装置及び画像表示方法をコンピュータに実行させるためのプログラム
JP4882445B2 (ja) 情報処理装置及びその起動方法
JP2013196476A (ja) データ処理装置およびメモリ制御装置
JP6909079B2 (ja) 記録装置及び記録方法
JP4761120B2 (ja) 電子機器、画像形成装置
JP2012234502A (ja) メモリ制御装置、画像処理装置、メモリ制御方法、メモリ制御プログラム及び記録媒体
JP2017084305A (ja) メモリを制御する制御装置及びメモリの省電力制御方法

Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 20140922

PG1501 Laying open of application
A201 Request for examination
PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 20150922

Comment text: Request for Examination of Application

Patent event code: PA02011R01I

Patent event date: 20140922

Comment text: Patent Application

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20160420

Patent event code: PE09021S01D

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20161026

Patent event code: PE09021S01D

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 20170425

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 20170721

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 20170724

End annual number: 3

Start annual number: 1

PG1601 Publication of registration
PR1001 Payment of annual fee

Payment date: 20200714

Start annual number: 4

End annual number: 4

PR1001 Payment of annual fee

Payment date: 20210628

Start annual number: 5

End annual number: 5

PR1001 Payment of annual fee

Payment date: 20220627

Start annual number: 6

End annual number: 6

PR1001 Payment of annual fee

Payment date: 20230622

Start annual number: 7

End annual number: 7

PR1001 Payment of annual fee

Payment date: 20240625

Start annual number: 8

End annual number: 8

PR1001 Payment of annual fee

Payment date: 20250630

Start annual number: 9

End annual number: 9