WO2017107164A1 - 异构混合内存架构的计算机系统及其控制方法、内存检测系统 - Google Patents

异构混合内存架构的计算机系统及其控制方法、内存检测系统 Download PDF

Info

Publication number
WO2017107164A1
WO2017107164A1 PCT/CN2015/098818 CN2015098818W WO2017107164A1 WO 2017107164 A1 WO2017107164 A1 WO 2017107164A1 CN 2015098818 W CN2015098818 W CN 2015098818W WO 2017107164 A1 WO2017107164 A1 WO 2017107164A1
Authority
WO
WIPO (PCT)
Prior art keywords
memory
unit
computer system
storage unit
volatile
Prior art date
Application number
PCT/CN2015/098818
Other languages
English (en)
French (fr)
Inventor
李杨
庞观士
徐成泽
沈航
陈志列
耿稳强
Original Assignee
研祥智能科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 研祥智能科技股份有限公司 filed Critical 研祥智能科技股份有限公司
Priority to PCT/CN2015/098818 priority Critical patent/WO2017107164A1/zh
Publication of WO2017107164A1 publication Critical patent/WO2017107164A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems

Definitions

  • the present invention relates to the field of computer technologies, and in particular, to a computer system of a heterogeneous hybrid memory architecture, a control method of a computer system, and a memory detection system.
  • NVM non-volatile memory
  • the BIOS Basic Input & Output System
  • the MRC Memory Reference Code
  • DRAM Dynamic Random Access Memory
  • Self-test and initialization of access memory In the heterogeneous mixed memory architecture of NVM+DRAM, to use NVM memory, the BIOS must also perform corresponding self-test and initialization on the NVM. NVM is not really intended
  • the non-volatile nature of the memory allows the NVM to be used as an external storage device in addition to the memory, so data, code and even the operating system can be stored in the NVM.
  • the traditional MRC cannot recognize NVM under the heterogeneous mixed memory architecture, and can not initialize and self-test the NVM.
  • the BIOS does not initialize the NVM, the operating system and application software cannot access the NVM, and the NVM is unavailable at this time.
  • the BIOS due to the non-volatility of NVM, data is stored in the NVM in general.
  • the BIOS cannot erase and write operations like DRAM, because it will cause data loss in the NVM.
  • the NVM application is mainly used as an external memory on the PCIE bus, as shown in Figure 4.
  • NVM is compared with a normal mechanical hard disk. The difference is that NVM is essentially a non-volatile storage device, and the CPU can directly access the NVM through the NVM controller.
  • the ordinary hard disk is a disk, which requires the rotation of a mechanical motor to drive the head to access various sectors of the disk. Therefore, the read and write speed of NVM is higher than that of accessing ordinary hard disks.
  • the traditional architecture determines that NVM is only used as an external storage device. During computer startup, the BIOS does not form a unified system memory report for NVM and DRAM. NVM cannot be used as memory.
  • a method of controlling the computer system and a memory detection system within the computer system are also provided.
  • a computer system of heterogeneous hybrid memory architecture comprising:
  • the memory unit includes a first SPD chip and is connected to the computer system through the DIMM interface; the first SPD chip includes storage capacity information of the memory unit;
  • non-volatile memory unit including a second SPD chip and connected to the computer system through the DIMM interface;
  • the second SPD chip includes a storage capacity and memory category information of the non-volatile storage unit;
  • the BIOS unit is configured to acquire capacity information of the second SPD chip during a power-on self-test phase, and form a system memory report together with the storage capacity information of the memory unit.
  • the non-volatile memory unit further includes a memory controller and a storage medium, the memory controller being interfaced with the DIMM and controlling reading and writing of the storage medium.
  • the storage medium is a resistive storage medium, a ferroelectric storage medium, or a phase change storage medium.
  • the non-volatile storage unit further includes a dynamic random access storage buffer module coupled to the storage controller.
  • the number of the non-volatile storage units is two or more, and the computer system is respectively connected to the computer system through the DIMM interface, and the BIOS unit acquires each non-volatile storage unit one by one in the power-on self-test phase.
  • the second SPD chip capacity information is provided.
  • a computer system control method for a heterogeneous hybrid memory architecture comprising the following steps:
  • the BIOS unit determines the type of the storage unit by reading the memory class information in the first SPD chip or the second SPD chip; if it is determined that the storage unit is a memory unit, performing a normal power-on self-test process; Capacity information of the volatile storage unit;
  • the second SPD chip further stores a data flag bit indicating whether the non-volatile memory unit contains data
  • the step of acquiring the capacity information of the current non-volatile memory unit includes:
  • the address space of the non-volatile memory unit is mapped into a contiguous address space after the end address of the memory unit.
  • system memory report also identifies an address segment that belongs to a memory unit and an address segment that belongs to a non-volatile memory unit.
  • a memory detection system based on the above computer system, running in the BIOS unit, comprising:
  • a memory detection module configured to detect whether a DIMM interface is connected to the storage unit, where the storage unit includes a memory unit and a non-volatile storage unit;
  • An identification module configured to read memory class information in the first SPD chip or the second SPD chip to determine a type of the storage unit
  • a non-volatile storage unit self-test module configured to determine whether the non-volatile storage unit contains data, and if so, perform integrity verification on the area containing the data; otherwise, perform an erase and write operation to verify Whether the non-volatile storage unit contains a bad block, and generates a self-test result and capacity information;
  • a system memory report module configured to map an address space of the non-volatile storage unit to a contiguous address space after an end address of the memory unit, and indicate a location belonging to the memory unit The address segment and the address segment belonging to the non-volatile memory unit.
  • the computer system, the control method, and the memory detection system of the heterogeneous hybrid memory architecture are added in the BIOS unit by mounting the nonvolatile storage unit under the memory controller and saving the memory type information by using the second SPD chip.
  • the non-volatile memory unit can be incorporated into the memory system during the power-on self-test phase, and read and write operations as memory during the subsequent system operation phase.
  • the non-volatile memory unit is much higher than the traditional disk in terms of its read and write speed, and the cost per unit of storage is much lower than that of the DRAM and other memory units, so that the entire computer system achieves a certain degree of read and write speed and cost. Balance.
  • 1 is a computer system of a heterogeneous hybrid memory architecture of an embodiment
  • FIG. 2 is a flow chart showing the control of a computer system of a heterogeneous hybrid memory architecture according to an embodiment
  • FIG. 3 is a block diagram of a memory detection system in a computer system of a heterogeneous hybrid memory architecture according to an embodiment
  • FIG 4 shows the application of the traditional NVM.
  • the heterogeneous hybrid memory architecture computer system 10 includes a memory unit 100, a non-volatile storage unit 200, and a BIOS unit 300. Both the memory unit 100 and the non-volatile memory unit 200 are connected to the computer system through a DIMM (Dual Inline Memory Modules) interface.
  • DIMM Dual Inline Memory Modules
  • Memory unit 100 is DRAM (Dynamic Random Access Memory) Memory).
  • the memory unit 100 is usually provided with an SPD (Serial Presence Detect) chip for storing configuration information of the DRAM, such as the number of P-Banks, the number of voltages, the number of row/column addresses, the bit width, and various main types. The operation timing and the like can also be used to store the storage capacity information of the memory unit 100.
  • the SPD chip provided on the memory unit 100 is referred to as a first SPD chip 110.
  • the non-volatile memory unit 200 is different from the volatile memory unit 100, which includes a non-volatile memory medium that reads and writes data in a manner different from that of a conventional magnetic disk.
  • Common non-volatile storage media include resistive storage media, ferroelectric storage media, or phase change storage media.
  • the nonvolatile memory unit 200 of the present embodiment may include any of the above nonvolatile storage media.
  • the non-volatile memory unit 200 is also coupled to the computer system via a DIMM interface.
  • the nonvolatile memory unit 200 includes a memory controller 210 and a storage medium 220 that is interfaced with the DIMM and controls reading and writing to the storage medium 220.
  • the non-volatile memory unit 200 can be mounted under the memory controller of the computer system.
  • the non-volatile memory unit 200 is also provided with an SPD chip, which is referred to as a second SPD chip 230 in this embodiment.
  • the second SPD chip 230 contains important information such as the model number, storage capacity, memory type, and manufacturer of the nonvolatile memory unit 200.
  • the memory category information is not included in the first SPD chip 110.
  • the number of nonvolatile memory cells 200 may be two or more.
  • the BIOS unit 300 holds a set of programs that are originally used to execute when the computer is powered on. Compared with the conventional BIOS unit, the BIOS unit 300 of the embodiment includes a detection code for the non-volatile memory unit 200 in addition to the normal memory detection code, and is used to acquire the second SPD chip during the power-on self-test phase.
  • the capacity information of 230 together with the storage capacity information of the memory unit 100, forms a system memory report.
  • BIOS unit 300 The second SPD chip capacity information of each non-volatile memory unit is acquired one by one in the power-on self-test phase.
  • the computer system 10 of the heterogeneous hybrid memory architecture described above is added to the BIOS unit 300 by causing the nonvolatile memory unit 200 to be mounted under the memory controller and storing the memory type information by using the second SPD chip.
  • the detection code of the detachable storage unit 200 can incorporate the non-volatile storage unit 200 into the memory system at the power-on self-test stage, and perform read and write operations as a memory in a subsequent system operation phase.
  • the non-volatile memory unit 200 is much higher in read/write speed than the conventional disk, and the cost per unit of storage is much lower than that of the DRAM and other memory units, so that the entire computer system achieves a certain read and write speed and cost. Balance of degree.
  • the non-volatile memory unit 200 further includes a dynamic random access storage buffer (DRAM buffer) module 240.
  • the dynamic random access storage buffer module 240 is coupled to the storage controller 210.
  • the dynamic random access storage buffer module 240 uses the dynamic random access storage medium to save data, and acts as a buffer when the operation speed demand is high.
  • the storage controller 210 first saves the operation result in the dynamic random access storage buffer module 240, and all the operations are completed. Thereafter, it is written into the nonvolatile storage medium 220.
  • a control method of a computer system of a heterogeneous hybrid memory architecture includes the following steps.
  • Step S101 The SMBus controller is initialized.
  • SMBus is the system management bus.
  • the BIOS program When executed after the computer is started, the CPU unit initializes the SMBus controller.
  • Each SPD chip is assigned a fixed address in the BIOS unit. The above initialization writes the address of the SPD chip to be detected in the SMBus controller.
  • Step S102 The next SPD address. If it is the first test, it is the first SPD address.
  • Step S103 SMBus read operation.
  • Step S104 determining whether the SPD chip has a response, if yes, executing step S105, otherwise executing step Step S102. If the SPD responds, it indicates that the storage unit (memory unit or non-volatile storage unit) is connected to the current memory slot (DIMM interface), and the next step can be performed; otherwise, the current memory slot is not connected to the storage unit, and the next one needs to be detected. SPD address.
  • the SPD chip may be the first SPD chip 110 or the second SPD chip 230.
  • Step S105 Read storage type information.
  • the BIOS unit 300 reads the memory class information in the first SPD chip 110 or the second SPD chip 230.
  • Step S106 determining whether it is a non-volatile storage unit, if yes, executing step S107, otherwise executing step S115.
  • the memory class information is saved in the second SPD chip 230, so whether the memory cell 100 or the nonvolatile memory cell 200 is inserted in the current memory slot can be determined according to whether the memory class information is read or not.
  • the detection code corresponding to the nonvolatile memory unit 200 that is, the following steps S107 to S109, is executed.
  • the conventional memory unit 100 i.e., DRAM
  • a conventional memory detecting step, step S115 is performed.
  • Step S107 determining whether there is data in the non-volatile storage unit, if yes, executing step S108, otherwise executing step S113.
  • Other useful data may be stored in the non-volatile memory unit 200 and needs to be determined.
  • the second SPD chip 230 further stores a data flag bit indicating whether the nonvolatile memory unit 200 contains data, and determines whether the nonvolatile memory unit contains data according to the value of the data flag bit.
  • Step S108 It is judged whether the data is complete, if yes, step S109 is performed, otherwise step S114 is performed. If data is stored in the non-volatile memory unit 200, it is also subjected to data integrity verification.
  • Step S109 Mapping the address space of the nonvolatile storage unit. Mainly to map the address space of the non-volatile memory unit 200 to the address space of the memory.
  • step S109 the capacity information of all the non-volatile memory cells that have been detected can be counted.
  • Step S110 It is judged whether the SPD traversal is over, if yes, step S111 is performed, otherwise step S102 is performed.
  • Step S111 Acquire address information of the memory unit. This step is performed during the normal self-test of the memory.
  • Step S112 Form a system memory report.
  • the address space of the nonvolatile memory unit 200 may be mapped into a continuous address space after the end address of the memory unit 100, and the memory The storage capacity information of the unit together form a system memory report.
  • the capacities of the plurality of nonvolatile memory cells 200 are sequentially allocated in consecutive address spaces after the end address of the memory cells 100.
  • system memory report also indicates an address segment belonging to the memory unit 100 and an address segment belonging to the nonvolatile memory unit 200.
  • the address segment belonging to the memory unit 100 can be prioritized to improve the writing speed.
  • Step S113 The non-volatile memory unit is initialized and self-tested. Specifically, an erase and write operation is performed to check whether the nonvolatile memory unit 200 contains a bad block, and a self-test result and capacity information are generated.
  • Step S114 Output prompt information.
  • the self-test information of the nonvolatile memory unit 200 may be output after the step S113 or the determination of the step S108 is NO.
  • Step S115 The power-on self-test process. That is, the POST process continues.
  • Step S116 Perform detection according to the memory reference code. Steps S115 to S116 are normal memory self-test processes, and are not described again.
  • a memory detection system 30 of a computer system of a heterogeneous hybrid memory architecture is provided.
  • the memory detection system 30 operates in the BIOS unit 300.
  • the memory detection system 30 includes a memory detection module 310, an identification module 320, a non-volatile storage unit self-test module 330, and a system memory report module 340.
  • the memory detection module 310 is configured to detect whether the DIMM interface is connected to the storage unit.
  • the storage unit includes a memory unit and a non-volatile storage unit. For the detection method, refer to the above steps S101 to S104.
  • the identification module 320 is configured to read memory class information in the first SPD chip or the second SPD chip to determine the type of the storage unit. For the identification method, reference may be made to the above step S105.
  • the non-volatile storage unit self-test module 330 is configured to determine whether the non-volatile storage unit contains data, and if so, perform integrity verification on the area containing the data; otherwise, perform an erase and write operation to verify Whether the non-volatile storage unit contains a bad block generates a self-test result and capacity information. Reference may be made to steps S106 to S108 and steps S113 to S114.
  • the system memory report module 340 is configured to map the address space of the non-volatile storage unit 200 to a contiguous address space after the end address of the memory unit, and indicate the address segment belonging to the memory unit and belong to the non-easy The address segment of the lossy memory unit. Reference may be made to step S112.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System (AREA)

Abstract

涉及一种异构混合内存架构的计算机系统(10)，包括：内存单元(100)，包括第一SPD芯片(110)，并通过DIMM接口接入计算机系统；所述第一SPD芯片(110)包括内存单元(100)的存储容量信息；非易失性存储单元(200)，包括第二SPD芯片(230)，并通过DIMM接口接入计算机系统；所述第二SPD芯片(230)包括非易失性存储单元(200)的存储容量和存储器类别信息；BIOS单元(300)，用于在上电自检阶段获取所述第二SPD芯片(230)的容量信息，与所述内存单元(100)的存储容量信息一起形成系统内存报表。还涉及一种该计算机系统(10)的控制方法以及一种该计算机系统(10)中的内存检测系统(30)。上述计算机系统(10)、控制方法以及内存检测系统(30)可以使整个计算机系统在读写速度和成本上取得一定程度的平衡。

Description

异构混合内存架构的计算机系统及其控制方法、内存检测系统 技术领域
本发明涉及计算机技术领域，特别是涉及一种异构混合内存架构的计算机系统、一种计算机系统的控制方法以及内存检测系统。
背景技术
针对云计算和大数据所表现出的增量速度快、时间局部性低等特点，使得以计算为中心的传统模式面临着内存容量有限、输入/输出压力大、缓存命中率低、数据处理的总体性能低等诸多挑战，难以取得性能、能耗与成本的最佳平衡，使得目前的计算机系统无法处理PB级以上的大数据。随着电阻存储器、铁电存储器、相变存储器等为代表的新兴非易失性存储介质(Non-Volatile Memory，NVM)技术的发展，使得传统的内存与存储分离的界限逐渐变得模糊，推进了存储技术的发展，为新型的内存与存储体系结构的产生打下了良好的基础。通过把新型的NVM和DRAM相结合，搭建异构混合内存架构是解决上述问题的理想选择。
计算机在POST(Power On Self-Test，上电自检)阶段，BIOS(Basic Input&Output System，基本输入输出系统)调用MRC(Memory Reference Code，内存参考代码)实现对DRAM(Dynamic Random Access Memory，动态随机访问存储器)的自检和初始化，在NVM+DRAM的异构混合内存架构下，要使用NVM存储器，BIOS还必须对NVM进行相应的自检和初始化。NVM并不是真正意 义上的内存，其非易失性使得NVM除了可以作为内存之外还可以作为外部存储设备使用，因而数据、代码乃至操作系统都可以存储在NVM中。传统的MRC在异构混合内存架构下，无法识别NVM，同时亦不能实现对NVM的初始化和自检。当BIOS没有对NVM做初始化时，操作系统、应用软件无法访问NVM，此时NVM是不可用的。同时，由于NVM的非易失性,一般NVM中存储有数据等资料，BIOS不能像对待DRAM那样进行擦除和写操作，因为这样会导致NVM中的资料丢失。
目前业界对NVM的应用，NVM主要还只是作为外部存储器挂在PCIE总线上，如图4所示。
NVM和普通机械硬盘相比较，区别是NVM本质上是一种非易失性的存储设备，CPU通过NVM控制器可以直接访问NVM。而普通硬盘是磁盘，需要机械马达的转动来驱动磁头去访问磁盘的各个扇区。因而NVM的读写速度比访问普通硬盘高一些。
传统的架构决定了NVM只是作为外部存储设备使用，计算机启动过程中，BIOS不会把NVM和DRAM形成统一的系统内存报表，NVM不能作为内存使用。
发明内容
基于此，有必要提供一种可将NVM作为内存使用的异构混合内存架构的计算机系统，可使整个计算机系统达到读写速度和成本的平衡。
此外还提供一种该计算机系统的控制方法和该计算机系统内的内存检测系统。
一种异构混合内存架构的计算机系统，包括：
内存单元，包括第一SPD芯片，并通过DIMM接口接入计算机系统；所述第一SPD芯片包括内存单元的存储容量信息；
非易失性存储单元，包括第二SPD芯片，并通过DIMM接口接入计算机系统；所述第二SPD芯片包括非易失性存储单元的存储容量和存储器类别信息；
BIOS单元，用于在上电自检阶段获取所述第二SPD芯片的容量信息，与所述内存单元的存储容量信息一起形成系统内存报表。
在其中一个实施例中，所述非易失性存储单元还包括存储控制器和存储介质，所述存储控制器与DIMM接口连接、并控制对存储介质的读写。
在其中一个实施例中，所述存储介质为电阻存储介质、铁电存储介质或相变存储介质。
在其中一个实施例中，所述非易失性存储单元还包括动态随机访问存储缓冲模块，与所述存储控制器连接。
在其中一个实施例中，所述非易失性存储单元的数量为两个以上，分别通过DIMM接口接入计算机系统，所述BIOS单元在上电自检阶段逐一获取各个非易失性存储单元的第二SPD芯片容量信息。
一种异构混合内存架构的计算机系统的控制方法，基于上述的计算机系统，包括如下步骤：
BIOS单元通过读取所述第一SPD芯片或第二SPD芯片中的存储器类别信息以判断存储单元的类型；若判断存储单元为内存单元，则执行正常的上电自检过程；否则获取当前非易失性存储单元的容量信息；
统计所有非易失性存储单元的容量信息，并与所述内存单元的存储容量信 息一起形成系统内存报表。
在其中一个实施例中，所述第二SPD芯片还保存表示非易失性存储单元是否包含数据的数据标志位，所述获取当前非易失性存储单元的容量信息的步骤包括：
根据所述数据标志位的值判断所述非易失性存储单元是否包含数据，若是，则对包含数据的区域进行完整性校验；否则，进行擦除和写入操作以检验所述非易失性存储单元是否包含坏块，生成自检结果和容量信息。
在其中一个实施例中，所述非易失性存储单元的地址空间映射到所述内存单元的结束地址之后的一段连续的地址空间中。
在其中一个实施例中，所述系统内存报表还标明属于内存单元的地址段和属于非易失性存储单元的地址段。
一种内存检测系统，基于上述的计算机系统，运行于所述BIOS单元中，包括：
内存侦测模块，用于侦测DIMM接口是否连接存储单元，所述存储单元包括内存单元和非易失性存储单元；
识别模块，用于读取所述第一SPD芯片或第二SPD芯片中的存储器类别信息以判断存储单元的类型；
非易失性存储单元自检模块，用于判断所述非易失性存储单元是否包含数据，若是，则对包含数据的区域进行完整性校验；否则，进行擦除和写入操作以检验所述非易失性存储单元是否包含坏块，生成自检结果和容量信息；
系统内存报表模块，用于将所述非易失性存储单元的地址空间映射到所述内存单元的结束地址之后的一段连续的地址空间中，并标明属于内存单元的地 址段和属于非易失性存储单元的地址段。
上述异构混合内存架构的计算机系统、控制方法以及内存检测系统，通过在使非易失性存储单元挂载在内存控制器下，并且利用第二SPD芯片保存存储器类型信息，在BIOS单元中添加对应于非易失性存储单元的检测功能，可以将非易失性存储单元在开机自检阶段就纳入内存体系，并在之后的系统运行阶段作为内存进行读写操作。而非易失性存储单元就其读写速度来说远高于传统的磁盘，同时单位存储量的成本又远低于DRAM等内存单元，使得整个计算机系统在读写速度和成本上取得一定程度的平衡。
附图说明
图1为一实施例的异构混合内存架构的计算机系统；
图2为一实施例的异构混合内存架构的计算机系统控制流程图；
图3为一实施例的异构混合内存架构的计算机系统中的内存检测系统模块图；
图4为传统的NVM的应用方式。
具体实施方式
如图1所示，为一实施例的异构混合内存架构的计算机系统。该异构混合内存架构的计算机系统10包括内存单元100、非易失性存储单元200和BIOS单元300。内存单元100和非易失性存储单元200均通过DIMM(Dual Inline Memory Modules，双列直插式存储模块)接口接入计算机系统。
内存单元100即DRAM(Dynamic Random Access Memory，动态随机访问 存储器)。内存单元100上通常设有SPD(Serial Presence Detect，串行存在检测)芯片，其用来存储DRAM的配置信息，例如P-Bank数量、电压、行地址/列地址数量、位宽以及各种主要操作时序等，另外还可保存内存单元100的存储容量信息。本实施例中，将内存单元100上所设有的SPD芯片称为第一SPD芯片110。
非易失性存储单元200不同于易失性的内存单元100，其包括非易失性(Non-Volatile)的存储介质，其读写数据的方式也不同于传统的磁盘。常见的非易失性存储介质包括电阻存储介质、铁电存储介质或相变存储介质。本实施例的非易失性存储单元200可以包括以上任何一种非易失性存储介质。参考图1，非易失性存储单元200也是通过DIMM接口接入计算机系统。具体地，非易失性存储单元200包括存储控制器210和存储介质220，存储控制器210与DIMM接口连接、并控制对存储介质220的读写。这样，非易失性存储单元200就可以挂载在计算机系统的内存控制器下。
类似的，非易失性存储单元200也设有SPD芯片，在本实施例中称为第二SPD芯片230。第二SPD芯片230中包含非易失性存储单元200的型号、存储容量、存储器类别以及制造商等重要信息。其中存储器类别信息是第一SPD芯片110中所不包括的。非易失性存储单元200的数量可以是两个以上。
BIOS单元300保存有在计算机开机时最初用来执行的一组程序。本实施例的BIOS单元300与传统的BIOS单元相比，除了包括正常的内存检测代码，还包括对非易失性存储单元200的检测代码，用于在上电自检阶段获取第二SPD芯片230的容量信息，并与内存单元100的存储容量信息一起形成系统内存报表。对于包含两个以上的非易失性存储单元200的计算机系统，BIOS单元300 在上电自检阶段逐一获取各个非易失性存储单元的第二SPD芯片容量信息。
上述异构混合内存架构的计算机系统10，通过在使非易失性存储单元200挂载在内存控制器下，并且利用第二SPD芯片保存存储器类型信息，在BIOS单元300中添加对应于非易失性存储单元200的检测代码，可以将非易失性存储单元200在开机自检阶段就纳入内存体系，并在之后的系统运行阶段作为内存进行读写操作。而非易失性存储单元200就其读写速度来说远高于传统的磁盘，同时单位存储量的成本又远低于DRAM等内存单元，使得整个计算机系统在读写速度和成本上取得一定程度的平衡。
进一步地，非易失性存储单元200还包括动态随机访问存储缓冲(DRAM缓冲)模块240。动态随机访问存储缓冲模块240与存储控制器210连接。动态随机访问存储缓冲模块240采用动态随机访问存储介质保存数据，在运算速度需求较高的场合充当缓冲，存储控制器210先将运算结果保存在动态随机访问存储缓冲模块240中，全部运算执行完成后，再写入非易失性存储介质220中。
基于上述的计算机系统10，结合图1和图2，提供一种异构混合内存架构的计算机系统的控制方法。该方法包括如下步骤。
步骤S101：SMBus控制器初始化。SMBus即为系统管理总线(system management bus)。当计算机启动后执行BIOS程序时，CPU单元对SMBus控制器进行初始化。BIOS单元中为各个SPD芯片分配了固定的地址，上述初始化即在SMBus控制器中写入需要检测的SPD芯片的地址。
步骤S102：下一个SPD地址。如果是首次检测，则为第一个SPD地址。
步骤S103：SMBus读操作。
步骤S104：判断SPD芯片是否有响应，是则执行步骤S105，否则执行步 骤S102。如果SPD有响应则表示当前内存槽(DIMM接口)上接有存储单元(内存单元或非易失性存储单元)，可以执行下一步操作；否则表示当前内存槽未接存储单元，需要检测下一个SPD地址。
上述步骤S101～S104中，SPD芯片可能是第一SPD芯片110或第二SPD芯片230。
步骤S105：读取存储类型信息。BIOS单元300读取所述第一SPD芯片110或第二SPD芯片230中的存储器类别信息。
步骤S106：判断是否为非易失性存储单元，是则执行步骤S107，否则执行步骤S115。根据上述实施例的说明，只有第二SPD芯片230中才保存存储器类别信息，因此可以根据是否读到该存储器类别信息判断当前内存槽内插入的是内存单元100还是非易失性存储单元200。如果是非易失性存储单元200，则执行对应于非易失性存储单元200的检测代码，也即下述的步骤S107～S109。如果是传统的内存单元100(即DRAM)，则执行传统的内存检测步骤，即步骤S115。
步骤S107：判断非易失性存储单元中是否有数据，是则执行步骤S108，否则执行步骤S113。非易失性存储单元200中可能存储有其他有用数据，需要进行判断。本实施例中，第二SPD芯片230还保存表示非易失性存储单元200是否包含数据的数据标志位，根据所述数据标志位的值判断所述非易失性存储单元是否包含数据。
步骤S108：判断数据是否完整，是则执行步骤S109，否则执行步骤S114。若非易失性存储单元200中存储有数据，还对其进行数据完整性校验。
步骤S109：将所述非易失性存储单元的地址空间进行映射。主要是将非易失性存储单元200的地址空间映射到内存的地址空间。
至步骤S109可统计当前已检测的所有非易失性存储单元的容量信息。
步骤S110：判断SPD遍历是否结束，是则执行步骤S111，否则执行步骤S102。
步骤S111：获取内存单元的地址信息。本步骤在内存的正常自检过程中执行。
步骤S112：形成系统内存报表。获得内存单元100和非易失性存储单元200的容量信息后，可以将非易失性存储单元200的地址空间映射到内存单元100的结束地址之后的一段连续的地址空间中，与所述内存单元的存储容量信息一起形成系统内存报表。对于多个非易失性存储单元200的情况，内存单元100的结束地址之后的连续地址空间内依次分配多个非易失性存储单元200的容量。
进一步地，所述系统内存报表还标明属于内存单元100的地址段和属于非易失性存储单元200的地址段。计算机系统在写数据时，若内存充裕，可优先考虑属于内存单元100的地址段，提高写入速度。
步骤S113：非易失性存储单元初始化、自检。具体为：进行擦除和写入操作以检验非易失性存储单元200是否包含坏块，生成自检结果和容量信息。
步骤S114：输出提示信息。可在步骤S113之后或步骤S108判断为否的情况下执行，输出非易失性存储单元200的自检信息。
步骤S115：上电自检过程。也即POST过程继续。
步骤S116：根据内存参考代码进行检测。步骤S115～S116为正常的内存自检过程，不再赘述。
基于上述的计算机系统10，结合图1和图3，提供一种异构混合内存架构的计算机系统的内存检测系统30，该内存检测系统30运行于BIOS单元300中。 该内存检测系统30包括内存侦测模块310、识别模块320、非易失性存储单元自检模块330以及系统内存报表模块340。
内存侦测模块310用于侦测DIMM接口是否连接存储单元。所述存储单元包括内存单元和非易失性存储单元。侦测方法可参考上述步骤S101～S104。
识别模块320用于读取所述第一SPD芯片或第二SPD芯片中的存储器类别信息以判断存储单元的类型。识别方法可参考上述步骤S105。
非易失性存储单元自检模块330用于判断所述非易失性存储单元是否包含数据，若是，则对包含数据的区域进行完整性校验；否则，进行擦除和写入操作以检验所述非易失性存储单元是否包含坏块，生成自检结果和容量信息。可参考步骤S106～S108以及步骤S113～S114。
系统内存报表模块340用于将所述非易失性存储单元200的地址空间映射到所述内存单元的结束地址之后的一段连续的地址空间中，并标明属于内存单元的地址段和属于非易失性存储单元的地址段。可参考步骤S112。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种异构混合内存架构的计算机系统，其特征在于，包括：
    内存单元，包括第一SPD芯片，并通过DIMM接口接入计算机系统；所述第一SPD芯片包括内存单元的存储容量信息；
    非易失性存储单元，包括第二SPD芯片，并通过DIMM接口接入计算机系统；所述第二SPD芯片包括非易失性存储单元的存储容量和存储器类别信息；
    BIOS单元，用于在上电自检阶段获取所述第二SPD芯片的容量信息，与所述内存单元的存储容量信息一起形成系统内存报表。
  2. 根据权利要求1所述的异构混合内存架构的计算机系统，其特征在于，所述非易失性存储单元还包括存储控制器和存储介质，所述存储控制器与DIMM接口连接、并控制对存储介质的读写。
  3. 根据权利要求2所述的异构混合内存架构的计算机系统，其特征在于，所述存储介质为电阻存储介质、铁电存储介质或相变存储介质。
  4. 根据权利要求2所述的异构混合内存架构的计算机系统，其特征在于，所述非易失性存储单元还包括动态随机访问存储缓冲模块，与所述存储控制器连接。
  5. 根据权利要求1所述的异构混合内存架构的计算机系统，其特征在于，所述非易失性存储单元的数量为两个以上，分别通过DIMM接口接入计算机系统，所述BIOS单元在上电自检阶段逐一获取各个非易失性存储单元的第二SPD芯片容量信息。
  6. 一种异构混合内存架构的计算机系统的控制方法，基于权利要求1所述的计算机系统，包括如下步骤：
    BIOS单元通过读取所述第一SPD芯片或第二SPD芯片中的存储器类别信息以判断存储单元的类型；若判断存储单元为内存单元，则执行正常的上电自检过程；否则获取当前非易失性存储单元的容量信息；
    统计所有非易失性存储单元的容量信息，并与所述内存单元的存储容量信息一起形成系统内存报表。
  7. 根据权利要求6所述的异构混合内存架构的计算机系统的控制方法，其特征在于，所述第二SPD芯片还保存表示非易失性存储单元是否包含数据的数据标志位，所述获取当前非易失性存储单元的容量信息的步骤包括：
    根据所述数据标志位的值判断所述非易失性存储单元是否包含数据，若是，则对包含数据的区域进行完整性校验；否则，进行擦除和写入操作以检验所述非易失性存储单元是否包含坏块，生成自检结果和容量信息。
  8. 根据权利要求6所述的异构混合内存架构的计算机系统的控制方法，其特征在于，所述非易失性存储单元的地址空间映射到所述内存单元的结束地址之后的一段连续的地址空间中。
  9. 根据权利要求6所述的异构混合内存架构的计算机系统的控制方法，其特征在于，所述系统内存报表还标明属于内存单元的地址段和属于非易失性存储单元的地址段。
  10. 一种内存检测系统，基于权利要求1所述的计算机系统，运行于所述BIOS单元中，其特征在于，包括：
    内存侦测模块，用于侦测DIMM接口是否连接存储单元，所述存储单元包括内存单元和非易失性存储单元；
    识别模块，用于读取所述第一SPD芯片或第二SPD芯片中的存储器类别信 息以判断存储单元的类型；
    非易失性存储单元自检模块，用于判断所述非易失性存储单元是否包含数据，若是，则对包含数据的区域进行完整性校验；否则，进行擦除和写入操作以检验所述非易失性存储单元是否包含坏块，生成自检结果和容量信息；
    系统内存报表模块，用于将所述非易失性存储单元的地址空间映射到所述内存单元的结束地址之后的一段连续的地址空间中，并标明属于内存单元的地址段和属于非易失性存储单元的地址段。
PCT/CN2015/098818 2015-12-25 2015-12-25 异构混合内存架构的计算机系统及其控制方法、内存检测系统 WO2017107164A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2015/098818 WO2017107164A1 (zh) 2015-12-25 2015-12-25 异构混合内存架构的计算机系统及其控制方法、内存检测系统

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2015/098818 WO2017107164A1 (zh) 2015-12-25 2015-12-25 异构混合内存架构的计算机系统及其控制方法、内存检测系统

Publications (1)

Publication Number Publication Date
WO2017107164A1 true WO2017107164A1 (zh) 2017-06-29

Family

ID=59088724

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/098818 WO2017107164A1 (zh) 2015-12-25 2015-12-25 异构混合内存架构的计算机系统及其控制方法、内存检测系统

Country Status (1)

Country Link
WO (1) WO2017107164A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112214448A (zh) * 2020-10-10 2021-01-12 中科声龙科技发展（北京）有限公司 异质集成工作量证明运算芯片的数据动态重构电路及方法
CN114816939A (zh) * 2022-05-31 2022-07-29 苏州浪潮智能科技有限公司 一种内存通信方法、系统、设备及介质

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8006062B1 (en) * 2007-05-10 2011-08-23 Nvidia Corporation Apparatus, system, and method for extended serial presence detect for memory performance optimization
CN103810112A (zh) * 2014-01-28 2014-05-21 华中科技大学 一种非易失性内存系统及其管理方法
CN103810113A (zh) * 2014-01-28 2014-05-21 华中科技大学 一种非易失存储器和动态随机存取存储器的融合内存系统
CN104360963A (zh) * 2014-11-26 2015-02-18 浪潮(北京)电子信息产业有限公司 一种面向内存计算的异构混合内存方法和装置
CN104464813A (zh) * 2013-09-25 2015-03-25 佳能株式会社 存储器控制设备、存储器控制方法及信息设备
CN105786716A (zh) * 2014-12-25 2016-07-20 研祥智能科技股份有限公司 异构混合内存架构的计算机系统及其控制方法、内存检测系统

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8006062B1 (en) * 2007-05-10 2011-08-23 Nvidia Corporation Apparatus, system, and method for extended serial presence detect for memory performance optimization
CN104464813A (zh) * 2013-09-25 2015-03-25 佳能株式会社 存储器控制设备、存储器控制方法及信息设备
CN103810112A (zh) * 2014-01-28 2014-05-21 华中科技大学 一种非易失性内存系统及其管理方法
CN103810113A (zh) * 2014-01-28 2014-05-21 华中科技大学 一种非易失存储器和动态随机存取存储器的融合内存系统
CN104360963A (zh) * 2014-11-26 2015-02-18 浪潮(北京)电子信息产业有限公司 一种面向内存计算的异构混合内存方法和装置
CN105786716A (zh) * 2014-12-25 2016-07-20 研祥智能科技股份有限公司 异构混合内存架构的计算机系统及其控制方法、内存检测系统

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112214448A (zh) * 2020-10-10 2021-01-12 中科声龙科技发展（北京）有限公司 异质集成工作量证明运算芯片的数据动态重构电路及方法
CN112214448B (zh) * 2020-10-10 2024-04-09 声龙(新加坡)私人有限公司 异质集成工作量证明运算芯片的数据动态重构电路及方法
CN114816939A (zh) * 2022-05-31 2022-07-29 苏州浪潮智能科技有限公司 一种内存通信方法、系统、设备及介质

Similar Documents

Publication Publication Date Title
TWI704487B (zh) 資料儲存設備及其操作方法
TWI703571B (zh) 數據儲存裝置及其操作方法
US9753849B2 (en) Methods for manufacturing and operating a memory device and a method for operating a system having the same
US8478963B2 (en) Method of dynamically switching partitions, memory card controller and memory card storage system
KR102585883B1 (ko) 메모리 시스템의 동작 방법 및 메모리 시스템
US11416177B2 (en) Memory sub-system storage mode control
CN107741913B (zh) 用来管理一记忆装置的方法、记忆装置与控制器
TWI719494B (zh) 用於控制不同類型儲存單元的方法及裝置
CN105786716A (zh) 异构混合内存架构的计算机系统及其控制方法、内存检测系统
US11157201B2 (en) Memory system and operating method thereof
US11282584B2 (en) Multi-chip package and method of testing the same
US11086636B2 (en) Data storage device and method for operating non-volatile memory
US20170123881A1 (en) Test method of volatile memory device embedded in electronic device
KR20210147696A (ko) 데이터 저장 장치 및 그것의 동작 방법
TWI679641B (zh) 非揮發性記憶體裝置和操作方法及包括其的資料存儲裝置
WO2017107164A1 (zh) 异构混合内存架构的计算机系统及其控制方法、内存检测系统
CN107219998B (zh) 数据存储装置及其操作方法
US10599562B2 (en) Nonvolatile memory device configured to be accessed without block address and method of operating the same
US20090182932A1 (en) Method for managing flash memory blocks and controller using the same
CN108628538B (zh) 一种NAND Flash中数据存储方法和装置
KR20170051124A (ko) 전자 장치에 내장된 휘발성 메모리 장치의 테스트 방법
KR20210034456A (ko) 메모리 컨트롤러, 스토리지 장치 및 상기 스토리지 장치의 동작 방법
US20240069776A1 (en) Super block management for efficient utilization
US20230041076A1 (en) Memory system and operating method thereof
TW202217817A (zh) 儲存裝置及其操作方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15911163

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15911163

Country of ref document: EP

Kind code of ref document: A1