KR101309549B1 - 얇은 반도체들에 대한 패널화된 후면 공정 - Google Patents

얇은 반도체들에 대한 패널화된 후면 공정 Download PDF

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KR101309549B1
KR101309549B1 KR1020117029271A KR20117029271A KR101309549B1 KR 101309549 B1 KR101309549 B1 KR 101309549B1 KR 1020117029271 A KR1020117029271 A KR 1020117029271A KR 20117029271 A KR20117029271 A KR 20117029271A KR 101309549 B1 KR101309549 B1 KR 101309549B1
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substrate
mold compound
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KR20120018787A (ko
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아빈드 찬드라세카란
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퀄컴 인코포레이티드
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Dicing (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
KR1020117029271A 2009-05-07 2010-05-07 얇은 반도체들에 대한 패널화된 후면 공정 Active KR101309549B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/437,168 US8294280B2 (en) 2009-05-07 2009-05-07 Panelized backside processing for thin semiconductors
US12/437,168 2009-05-07
PCT/US2010/034096 WO2010129903A1 (en) 2009-05-07 2010-05-07 Panelized backside processing for thin semiconductors

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Publication Number Publication Date
KR20120018787A KR20120018787A (ko) 2012-03-05
KR101309549B1 true KR101309549B1 (ko) 2013-09-24

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US (2) US8294280B2 (enExample)
EP (1) EP2427909B1 (enExample)
JP (1) JP5605958B2 (enExample)
KR (1) KR101309549B1 (enExample)
CN (2) CN106129000A (enExample)
ES (1) ES2900265T3 (enExample)
TW (1) TW201118937A (enExample)
WO (1) WO2010129903A1 (enExample)

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US8294280B2 (en) 2009-05-07 2012-10-23 Qualcomm Incorporated Panelized backside processing for thin semiconductors
US8541886B2 (en) * 2010-03-09 2013-09-24 Stats Chippac Ltd. Integrated circuit packaging system with via and method of manufacture thereof
US9230894B2 (en) * 2012-05-02 2016-01-05 Infineon Technologies Ag Methods for manufacturing a chip package
US8964888B2 (en) * 2012-08-29 2015-02-24 Qualcomm Incorporated System and method of generating a pre-emphasis pulse
US20150008566A1 (en) * 2013-07-02 2015-01-08 Texas Instruments Incorporated Method and structure of panelized packaging of semiconductor devices
US9257341B2 (en) 2013-07-02 2016-02-09 Texas Instruments Incorporated Method and structure of packaging semiconductor devices
US11239199B2 (en) 2015-12-26 2022-02-01 Intel Corporation Package stacking using chip to wafer bonding
DE102016108000B3 (de) * 2016-04-29 2016-12-15 Danfoss Silicon Power Gmbh Verfahren zum stoffschlüssigen Verbinden einer ersten Komponente eines Leistungshalbleitermoduls mit einer zweiten Komponente eines Leistungshalbleitermoduls
US10566267B2 (en) 2017-10-05 2020-02-18 Texas Instruments Incorporated Die attach surface copper layer with protective layer for microelectronic devices
US10879144B2 (en) 2018-08-14 2020-12-29 Texas Instruments Incorporated Semiconductor package with multilayer mold
US10643957B2 (en) 2018-08-27 2020-05-05 Nxp B.V. Conformal dummy die
US11114410B2 (en) 2019-11-27 2021-09-07 International Business Machines Corporation Multi-chip package structures formed by joining chips to pre-positioned chip interconnect bridge devices
US11342246B2 (en) * 2020-07-21 2022-05-24 Qualcomm Incorporated Multi-terminal integrated passive devices embedded on die and a method for fabricating the multi-terminal integrated passive devices
CN111739840B (zh) * 2020-07-24 2023-04-11 联合微电子中心有限责任公司 一种硅转接板的制备方法及硅转接板的封装结构

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040113275A1 (en) * 2002-10-08 2004-06-17 Chippac, Inc. Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package
US20070126085A1 (en) * 2005-12-02 2007-06-07 Nec Electronics Corporation Semiconductor device and method of manufacturing the same
KR20080068334A (ko) * 2007-01-19 2008-07-23 오태성 주석 비아 또는 솔더 비아와 이의 접속부를 구비한 칩 스택패키지 및 그 제조방법

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6010392A (en) * 1998-02-17 2000-01-04 International Business Machines Corporation Die thinning apparatus
JP3339838B2 (ja) * 1999-06-07 2002-10-28 ローム株式会社 半導体装置およびその製造方法
JP2001144218A (ja) * 1999-11-17 2001-05-25 Sony Corp 半導体装置及び半導体装置の製造方法
US6444576B1 (en) * 2000-06-16 2002-09-03 Chartered Semiconductor Manufacturing, Ltd. Three dimensional IC package module
JP3530149B2 (ja) * 2001-05-21 2004-05-24 新光電気工業株式会社 配線基板の製造方法及び半導体装置
KR100394808B1 (ko) * 2001-07-19 2003-08-14 삼성전자주식회사 웨이퍼 레벨 적층 칩 패키지 및 그 제조 방법
US6867501B2 (en) 2001-11-01 2005-03-15 Rohm Co., Ltd. Semiconductor device and method for manufacturing same
JP3893268B2 (ja) * 2001-11-02 2007-03-14 ローム株式会社 半導体装置の製造方法
JP4056854B2 (ja) * 2002-11-05 2008-03-05 新光電気工業株式会社 半導体装置の製造方法
JP4441328B2 (ja) * 2004-05-25 2010-03-31 株式会社ルネサステクノロジ 半導体装置及びその製造方法
JP5052130B2 (ja) 2004-06-04 2012-10-17 カミヤチョウ アイピー ホールディングス 三次元積層構造を持つ半導体装置及びその製造方法
JP4434977B2 (ja) * 2005-02-02 2010-03-17 株式会社東芝 半導体装置及びその製造方法
JP2007180529A (ja) * 2005-12-02 2007-07-12 Nec Electronics Corp 半導体装置およびその製造方法
JP2007317822A (ja) * 2006-05-25 2007-12-06 Sony Corp 基板処理方法及び半導体装置の製造方法
US7901989B2 (en) * 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
US8035207B2 (en) * 2006-12-30 2011-10-11 Stats Chippac Ltd. Stackable integrated circuit package system with recess
JP2008177504A (ja) * 2007-01-22 2008-07-31 Toyobo Co Ltd 半導体パッケージ
US8367471B2 (en) * 2007-06-15 2013-02-05 Micron Technology, Inc. Semiconductor assemblies, stacked semiconductor devices, and methods of manufacturing semiconductor assemblies and stacked semiconductor devices
SG149726A1 (en) * 2007-07-24 2009-02-27 Micron Technology Inc Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
US20100109169A1 (en) * 2008-04-29 2010-05-06 United Test And Assembly Center Ltd Semiconductor package and method of making the same
US8294280B2 (en) 2009-05-07 2012-10-23 Qualcomm Incorporated Panelized backside processing for thin semiconductors

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040113275A1 (en) * 2002-10-08 2004-06-17 Chippac, Inc. Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package
US20070126085A1 (en) * 2005-12-02 2007-06-07 Nec Electronics Corporation Semiconductor device and method of manufacturing the same
KR20080068334A (ko) * 2007-01-19 2008-07-23 오태성 주석 비아 또는 솔더 비아와 이의 접속부를 구비한 칩 스택패키지 및 그 제조방법

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TW201118937A (en) 2011-06-01
US20120040497A1 (en) 2012-02-16
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