CN106129000A - 用于薄半导体的平板化背侧处理 - Google Patents

用于薄半导体的平板化背侧处理 Download PDF

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Publication number
CN106129000A
CN106129000A CN201610693974.1A CN201610693974A CN106129000A CN 106129000 A CN106129000 A CN 106129000A CN 201610693974 A CN201610693974 A CN 201610693974A CN 106129000 A CN106129000 A CN 106129000A
Authority
CN
China
Prior art keywords
die
molding compound
tier
substrate
applying
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610693974.1A
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English (en)
Chinese (zh)
Inventor
阿尔温德·钱德拉舍卡朗
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN106129000A publication Critical patent/CN106129000A/zh
Pending legal-status Critical Current

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Classifications

    • H10W90/00—
    • H10W20/023—
    • H10W20/0245—
    • H10W74/00—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H10W70/099—
    • H10W72/012—
    • H10W72/01204—
    • H10W72/0198—
    • H10W72/072—
    • H10W72/07251—
    • H10W72/20—
    • H10W72/237—
    • H10W72/241—
    • H10W72/244—
    • H10W72/248—
    • H10W72/874—
    • H10W72/90—
    • H10W72/923—
    • H10W72/9413—
    • H10W72/951—
    • H10W74/142—
    • H10W90/22—
    • H10W90/28—
    • H10W90/297—
    • H10W90/722—
    • H10W90/724—

Landscapes

  • Dicing (AREA)
  • Engineering & Computer Science (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Manufacturing & Machinery (AREA)
CN201610693974.1A 2009-05-07 2010-05-07 用于薄半导体的平板化背侧处理 Pending CN106129000A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/437,168 US8294280B2 (en) 2009-05-07 2009-05-07 Panelized backside processing for thin semiconductors
US12/437,168 2009-05-07
CN201080020194.1A CN102422415B (zh) 2009-05-07 2010-05-07 用于薄半导体的平板化背侧处理

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CN201080020194.1A Division CN102422415B (zh) 2009-05-07 2010-05-07 用于薄半导体的平板化背侧处理

Publications (1)

Publication Number Publication Date
CN106129000A true CN106129000A (zh) 2016-11-16

Family

ID=42340979

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201610693974.1A Pending CN106129000A (zh) 2009-05-07 2010-05-07 用于薄半导体的平板化背侧处理
CN201080020194.1A Active CN102422415B (zh) 2009-05-07 2010-05-07 用于薄半导体的平板化背侧处理

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN201080020194.1A Active CN102422415B (zh) 2009-05-07 2010-05-07 用于薄半导体的平板化背侧处理

Country Status (8)

Country Link
US (2) US8294280B2 (enExample)
EP (1) EP2427909B1 (enExample)
JP (1) JP5605958B2 (enExample)
KR (1) KR101309549B1 (enExample)
CN (2) CN106129000A (enExample)
ES (1) ES2900265T3 (enExample)
TW (1) TW201118937A (enExample)
WO (1) WO2010129903A1 (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8294280B2 (en) 2009-05-07 2012-10-23 Qualcomm Incorporated Panelized backside processing for thin semiconductors
US8541886B2 (en) * 2010-03-09 2013-09-24 Stats Chippac Ltd. Integrated circuit packaging system with via and method of manufacture thereof
US9230894B2 (en) * 2012-05-02 2016-01-05 Infineon Technologies Ag Methods for manufacturing a chip package
US8964888B2 (en) * 2012-08-29 2015-02-24 Qualcomm Incorporated System and method of generating a pre-emphasis pulse
US9257341B2 (en) 2013-07-02 2016-02-09 Texas Instruments Incorporated Method and structure of packaging semiconductor devices
US20150008566A1 (en) * 2013-07-02 2015-01-08 Texas Instruments Incorporated Method and structure of panelized packaging of semiconductor devices
WO2017111836A1 (en) * 2015-12-26 2017-06-29 Intel IP Corporation Package stacking using chip to wafer bonding
DE102016108000B3 (de) * 2016-04-29 2016-12-15 Danfoss Silicon Power Gmbh Verfahren zum stoffschlüssigen Verbinden einer ersten Komponente eines Leistungshalbleitermoduls mit einer zweiten Komponente eines Leistungshalbleitermoduls
US10566267B2 (en) 2017-10-05 2020-02-18 Texas Instruments Incorporated Die attach surface copper layer with protective layer for microelectronic devices
US10879144B2 (en) 2018-08-14 2020-12-29 Texas Instruments Incorporated Semiconductor package with multilayer mold
US10643957B2 (en) 2018-08-27 2020-05-05 Nxp B.V. Conformal dummy die
US11114410B2 (en) 2019-11-27 2021-09-07 International Business Machines Corporation Multi-chip package structures formed by joining chips to pre-positioned chip interconnect bridge devices
US11342246B2 (en) * 2020-07-21 2022-05-24 Qualcomm Incorporated Multi-terminal integrated passive devices embedded on die and a method for fabricating the multi-terminal integrated passive devices
CN111739840B (zh) * 2020-07-24 2023-04-11 联合微电子中心有限责任公司 一种硅转接板的制备方法及硅转接板的封装结构

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020155692A1 (en) * 2000-06-16 2002-10-24 Chartered Semiconductor Manufacturing Ltd. Three dimensional TC package module
US20030017647A1 (en) * 2001-07-19 2003-01-23 Samsung Electronics Co., Ltd. Wafer level stack chip package and method for manufacturing same
US20040115867A1 (en) * 2001-11-01 2004-06-17 Kazutaka Shibata Semiconductor device and method for manufacturing same
CN101079372A (zh) * 2006-05-25 2007-11-28 索尼株式会社 基板处理方法和半导体装置的制造方法
WO2008157001A1 (en) * 2007-06-15 2008-12-24 Micron Technology, Inc. Semiconductor assemblies, stacked semiconductor devices, and methods of manufacturing semiconductor assemblies and stacked semiconductor devices
US20090026600A1 (en) * 2007-07-24 2009-01-29 Micron Technology, Inc. Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6010392A (en) * 1998-02-17 2000-01-04 International Business Machines Corporation Die thinning apparatus
JP3339838B2 (ja) * 1999-06-07 2002-10-28 ローム株式会社 半導体装置およびその製造方法
JP2001144218A (ja) * 1999-11-17 2001-05-25 Sony Corp 半導体装置及び半導体装置の製造方法
JP3530149B2 (ja) * 2001-05-21 2004-05-24 新光電気工業株式会社 配線基板の製造方法及び半導体装置
JP3893268B2 (ja) * 2001-11-02 2007-03-14 ローム株式会社 半導体装置の製造方法
US7045887B2 (en) * 2002-10-08 2006-05-16 Chippac, Inc. Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package
JP4056854B2 (ja) * 2002-11-05 2008-03-05 新光電気工業株式会社 半導体装置の製造方法
JP4441328B2 (ja) * 2004-05-25 2010-03-31 株式会社ルネサステクノロジ 半導体装置及びその製造方法
JP5052130B2 (ja) * 2004-06-04 2012-10-17 カミヤチョウ アイピー ホールディングス 三次元積層構造を持つ半導体装置及びその製造方法
JP4434977B2 (ja) * 2005-02-02 2010-03-17 株式会社東芝 半導体装置及びその製造方法
JP2007180529A (ja) * 2005-12-02 2007-07-12 Nec Electronics Corp 半導体装置およびその製造方法
US20070126085A1 (en) 2005-12-02 2007-06-07 Nec Electronics Corporation Semiconductor device and method of manufacturing the same
US7901989B2 (en) * 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
US8035207B2 (en) * 2006-12-30 2011-10-11 Stats Chippac Ltd. Stackable integrated circuit package system with recess
KR20080068334A (ko) 2007-01-19 2008-07-23 오태성 주석 비아 또는 솔더 비아와 이의 접속부를 구비한 칩 스택패키지 및 그 제조방법
JP2008177504A (ja) * 2007-01-22 2008-07-31 Toyobo Co Ltd 半導体パッケージ
US20100109169A1 (en) * 2008-04-29 2010-05-06 United Test And Assembly Center Ltd Semiconductor package and method of making the same
US8294280B2 (en) 2009-05-07 2012-10-23 Qualcomm Incorporated Panelized backside processing for thin semiconductors

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020155692A1 (en) * 2000-06-16 2002-10-24 Chartered Semiconductor Manufacturing Ltd. Three dimensional TC package module
US20030017647A1 (en) * 2001-07-19 2003-01-23 Samsung Electronics Co., Ltd. Wafer level stack chip package and method for manufacturing same
US20040115867A1 (en) * 2001-11-01 2004-06-17 Kazutaka Shibata Semiconductor device and method for manufacturing same
CN101079372A (zh) * 2006-05-25 2007-11-28 索尼株式会社 基板处理方法和半导体装置的制造方法
WO2008157001A1 (en) * 2007-06-15 2008-12-24 Micron Technology, Inc. Semiconductor assemblies, stacked semiconductor devices, and methods of manufacturing semiconductor assemblies and stacked semiconductor devices
US20090026600A1 (en) * 2007-07-24 2009-01-29 Micron Technology, Inc. Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods

Also Published As

Publication number Publication date
US20120040497A1 (en) 2012-02-16
CN102422415A (zh) 2012-04-18
US8294280B2 (en) 2012-10-23
JP5605958B2 (ja) 2014-10-15
EP2427909B1 (en) 2021-11-24
EP2427909A1 (en) 2012-03-14
US20100283160A1 (en) 2010-11-11
ES2900265T3 (es) 2022-03-16
JP2012526400A (ja) 2012-10-25
KR20120018787A (ko) 2012-03-05
KR101309549B1 (ko) 2013-09-24
US9252128B2 (en) 2016-02-02
WO2010129903A1 (en) 2010-11-11
CN102422415B (zh) 2016-09-07
TW201118937A (en) 2011-06-01

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Application publication date: 20161116