CN102422415A - 用于薄半导体的平板化背侧处理 - Google Patents

用于薄半导体的平板化背侧处理 Download PDF

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CN102422415A
CN102422415A CN2010800201941A CN201080020194A CN102422415A CN 102422415 A CN102422415 A CN 102422415A CN 2010800201941 A CN2010800201941 A CN 2010800201941A CN 201080020194 A CN201080020194 A CN 201080020194A CN 102422415 A CN102422415 A CN 102422415A
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nude film
mold compound
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liner panel
wafer
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CN102422415B (zh
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阿尔温德·钱德拉舍卡朗
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Qualcomm Inc
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Qualcomm Inc
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract

本发明揭示一种半导体制造方法，其包括将第一裸片附接到衬底面板。所述方法还包括在将所述第一裸片附接到所述衬底面板之后将模制化合物涂覆到所述第一裸片及所述衬底面板。所述方法进一步包括在涂覆所述模制化合物之后使所述第一裸片及所述模制化合物薄化。在薄化之前将所述裸片附接到所述衬底面板免除在处理薄半导体时使用载体晶片。

Description

用于薄半导体的平板化背侧处理
技术领域
本发明大体来说涉及集成电路(IC)。更具体来说，本发明涉及制造集成电路。
背景技术
半导体裸片包括晶体管与制造于衬底上的作用层中的其它组件的集合。通常，这些衬底为半导体材料，且特定来说为硅。另外，按照惯例，这些衬底厚于为获得所要装置行为所必需的厚度。按照惯例，所述层沉积于半导体晶片上，所述半导体晶片经单一化或经分割以形成诸多半导体裸片。
厚衬底在超出晶体管行为范围的半导体制造期间具有优点。在晶片及/或裸片的制造期间，衬底经受许多工艺、高温，及工具乃至制造地点之间的转移。在这些转移期间，衬底可能断裂，从而导致时间及资源的损失。厚衬底较不可能在制造期间断裂。
沉积于衬底上的材料可能会具有与衬底不同的应力，从而导致不平衡的应力。当衬底与所沉积材料之间的应力不平衡时，衬底可能翘曲或弯曲以达到一平衡应力。厚衬底能够比薄衬底更好地使由所沉积材料强加的应力平衡。已按照惯例通过用粘合剂将薄衬底附接到厚支撑衬底来解决关于在制造期间使用薄衬底的问题。所述支撑衬底被称作载体晶片。在完成制造过程的薄衬底经受破裂风险的部分之后，拆离所述载体晶片。
由于若干原因，使用载体晶片为不合需要的。所述载体晶片增加了制造成本，但未增加最终产品的有形价值。另外，将载体晶片附接到薄衬底的粘合剂会将残余物留在半导体晶片的薄衬底上。尽管载体晶片提供了制造期间的稳定性，但从载体晶片释放薄衬底提出了制造挑战。
使用薄衬底制造的一个实例是堆叠式IC的构造。堆叠式IC通过垂直地堆叠裸片而增大了装置功能性且减小了裸片大小。类似于使较多办公空间适配于较小土地面积的高层塔式大楼，堆叠式IC为晶体管及其它组件提供更多空间，同时占用相同面积。
在堆叠式IC中，第二裸片堆叠于第一裸片上，从而允许构造扩展成三维(3D)构造。堆叠式IC允许具有大量组件的产品适配小的形状因子。半导体裸片的组件密度为裸片中的组件的数目除以裸片面积。举例来说，将一裸片堆叠于一等同裸片上导致相同面积中的组件的数目大致加倍，以使组件密度加倍。当将第二裸片堆叠于第一裸片上时，所述两个裸片共享同一封装且经由所述封装与外部装置通信。
按照惯例，第二裸片通过位于第一裸片中的穿硅通孔而耦合到封装及外部装置。部分地基于所选择的制造技术，穿硅通孔的纵横比为受限制的。结果，第一裸片的高度受限制，以便确保穿硅通孔可延伸第一裸片的整个高度。穿硅通孔应延伸所述整个高度以获得从封装衬底到第二裸片的导电路径。随着第一裸片的高度减小以适应穿硅通孔制造，第一裸片的结构强度受到损失。
按照惯例，制造堆叠式IC包括在使第一裸片薄化之前将第一裸片附接到用于支撑的载体晶片。接着使所述第一裸片薄化以适应所述穿硅通孔的高度。在薄化之后应从载体晶片释放第一裸片的晶片，以封装堆叠式IC。然而，一旦从载体晶片释放，第一裸片便可能在第一裸片的衬底与裸片中的任何作用层之间具有不平衡应力。
因此，需要薄衬底的半导体制造，所述半导体制造减小了在不使用载体晶片的情况下所述薄衬底所遭受的风险。
发明内容
根据本发明的一个方面，一种半导体制造方法包括将第一裸片附接到衬底面板。所述方法还包括在将所述第一裸片附接到所述衬底面板之后将模制化合物涂覆到所述第一裸片及所述衬底面板。所述方法进一步包括在涂覆所述模制化合物之后使所述第一裸片及所述模制化合物薄化。
根据本发明的另一方面，一种半导体制造方法包括将一晶片分割成第一层裸片。所述方法还包括将所述第一层裸片附接到衬底面板。所述方法进一步包括将第一模制化合物涂覆到所述第一层裸片及所述衬底面板。所述方法还包括背面研磨所述第一层裸片及所述第一模制化合物。所述方法又还包括将第二层裸片附接到所述第一层裸片。所述方法进一步包括将第二模制化合物涂覆到所述第一层裸片及所述第二层裸片。
根据本发明的又一方面，一种半导体装置包括衬底面板。所述装置还包括附接于所述衬底面板上的第一裸片。所述装置进一步包括部分地环绕所述第一裸片且与所述衬底面板齐平的模制化合物。
根据本发明的另一方面，一种半导体装置包括用于电子处理的装置。所述装置还包括用于将所述用于电子处理的装置固定于适当位置的装置。所述装置进一步包括用于封装所述用于电子处理的装置的装置，其与所述用于固定的装置及所述用于电子处理的装置齐平。
前文已相当广泛地概述了本发明的特征及技术优点以便可更好地理解以下实施方式。下文中将描述形成本发明的权利要求书的主题的额外特征及优点。所属领域的技术人员应了解，所揭示的概念及特定实施例可容易地用作用于修改或设计其它结构的基础，所述其它结构是用于进行本发明的相同目的。所属领域的技术人员还应认识到，这些等效构造并不脱离如在所附权利要求书中所阐述的本发明的技术。当结合随附图式考虑时，从以下描述将更好地理解被视为本发明所特有的新颖特征(关于其组织及操作方法两者)连同其它目标及优点。然而，应明确地理解，各图中的每一者是仅出于说明及描述目的而提供且并不既定作为对本发明的限制的界定。
附图说明
为了更完整地理解本发明，现参考结合随附图式进行的以下描述。
图1为展示可有利地使用本发明的实施例的示范性无线通信系统的框图。
图2为说明针对如下文所揭示的半导体组件的电路、布局及逻辑设计而使用的设计工作站的框图。
图3为说明堆叠式IC的框图。
图4为说明处于张应力下的裸片的框图。
图5为说明常规堆叠式IC制造的流程图。
图6A到图6K为说明常规堆叠式IC制造过程的框图。
图7为说明根据一个实施例的用于制造IC的示范性工艺的流程图。
图8为说明根据一个实施例的用于制造堆叠式IC的示范性工艺的流程图。
图9A到图9L为说明根据一个实施例的示范性堆叠式IC制造过程的框图。
具体实施方式
图1为展示可有利地使用本发明的实施例的示范性无线通信系统100的框图。出于说明的目的，图1展示三个远程单元120、130及150以及两个基站140。应认识到，典型的无线通信系统可具有更多远程单元及基站。远程单元120、130及150包括IC装置125A、125B及125C，其包括通过本文所揭示的工艺所制造的电路。应认识到，含有IC的任何装置还可包括具有所揭示特征的半导体组件及/或通过本文中所揭示的工艺制造的组件，包括基站、开关装置及网络设备。图1展示从基站140到远程单元120、130及150的前向链路信号180及从远程单元120、130及150到基站140的反向链路信号190。
在图1中，将远程单元120展示为移动电话，将远程单元130展示为便携式计算机，且将远程单元150展示为无线本地环路系统中的固定位置远程单元。举例来说，所述远程单元可为例如以下各者的装置：音乐播放器、视频播放器、娱乐单元、导航装置、通信装置、个人数字助理(PDA)、固定位置数据单元，及计算机。尽管图1说明根据本发明的教示的远程单元，但本发明并不限于这些示范性说明的单元。如以下所描述，本发明可适合用于包括半导体组件的任何装置中。
图2为说明针对如以下所揭示的半导体组件的电路、布局及逻辑设计而使用的设计工作站的框图。设计工作站200包括硬盘201，所述硬盘201含有操作系统软件、支持文件及例如Cadence或OrCAD的设计软件。设计工作站200还包括显示器以协助电路210或半导体组件212(例如，晶片或裸片)的设计。提供存储媒体204用于以有形方式存储电路设计210或半导体组件212。电路设计210或半导体组件212可以例如GDSII或GERBER的文件格式存储于存储媒体204上。存储媒体204可为CD-ROM、DVD、硬盘、快闪存储器或其它适当装置。此外，设计工作站200包括驱动设备203，其用于接受来自存储媒体204的输入或将输出写入到存储媒体204。
记录于存储媒体204上的数据可指定逻辑电路配置、用于光刻掩模的图案数据，或用于串行写入工具(例如，电子束光刻)的掩模图案数据。所述数据可进一步包括例如与逻辑模拟相关联的时序图或网络电路等逻辑验证数据。将数据提供于存储媒体204上通过减小用于设计半导体晶片的过程的数目来协助电路设计210或半导体组件212的设计。
图3为说明堆叠式IC的框图。堆叠式IC 300包括封装衬底310。封装衬底310经由封装连接件322(例如，排列成球状栅格阵列的凸块)而耦合到第一层裸片320。或者，可使用引脚或其它合适的封装连接件。第二层裸片330经由封装连接件332(例如，排列成球状栅格阵列的凸块)耦合到第一层裸片320。第一层裸片320包括穿硅通孔324。穿硅通孔324延伸第一层裸片320的整个高度，且将封装衬底310耦合到封装连接件332以允许从封装衬底310到第一层裸片320或第二层裸片330的通信。可进一步将额外裸片(未图示)堆叠于第二层裸片330上。
例如堆叠式IC 300的堆叠式IC允许经由3D堆叠制造比可在2D IC上实现的密度高的密度的IC。举例来说，第二层裸片330可为存储器或高速缓冲存储器装置，且第一层裸片320可为处理器或其它逻辑电路。微处理器的裸片面积的大部分是由L2高速缓冲存储器占用。将高速缓冲存储器堆叠于逻辑电路上可减小微处理器的裸片大小。或者，可将位于与微处理器分开的裸片上的DRAM组件堆叠于微处理器上。将DRAM组件堆叠于微处理器上可减小主机板上的空间约束。另外，更接近于微处理器来定位DRAM组件可减小等待时间，且允许使用增加到DRAM组件的带宽(例如，较高的时钟速率)的方法。由于至少这些原因，预期可使用堆叠式IC实现的组件的较高密度，以支持将来IC的开发。
当第二层裸片330附接到第一层裸片320时，可能由于置放于第一层裸片320上所引起的物理力而发生损坏。第一层裸片320的厚度对应于其耐受这些物理力的机械强度。因此，当使第一层裸片320经薄化以暴露穿硅通孔324时，在第二层裸片330的附接期间更有可能发生对第一层裸片320的损坏。
图4为说明处于张应力下的裸片的框图。裸片400具有衬底412及作用层414。举例来说，衬底412可为硅或其它半导体材料。作用层414可包括例如晶体管等组件。作用层414还可包括互连件及通孔以将所述组件耦合到外部装置(未图式)。穿硅通孔416位于衬底412中，以允许衬底412的前侧413与衬底412的背侧411之间的耦合。举例来说，裸片400可为安装于封装衬底(未图示)上的堆叠式IC中的第一层。在此状况下，穿硅通孔416可将堆叠式IC的第二层耦合到所述封装衬底。
穿硅通孔416是通过例如反应性离子蚀刻、湿式蚀刻或激光钻孔等蚀刻技术来形成。穿硅通孔416的高度受限制，且部分地由穿硅通孔416的宽度来确定。举例来说，蚀刻工艺可具有10∶1的蚀刻比率，其指示所述蚀刻的深度仅可为穿硅通孔416的宽度的十倍。在此状况下，1μm的穿硅通孔可被蚀刻10μm深。因此，衬底412的高度应小于选定蚀刻工艺及穿硅通孔416的宽度所允许的高度。
衬底412的机械强度与衬底412的高度成比例。因此，减小衬底412的高度以允许穿硅通孔416从前侧413延伸到背侧411减小了衬底412的机械强度。作用层414在衬底412的薄化期间保留固定高度。因此，衬底412具有较小强度来支撑无关于衬底412的高度而在作用层414中逐步形成的相同水平的应力。视组成作用层414的膜的数目及类型而定，作用层414中的应力可为残余的压缩应力或残余的张应力。如果在衬底412上存在净残余压缩应力，则衬底412将倾向于向外推挤且整个组合件将呈皱眉状弯曲。如果在衬底412上存在净残余张应力，则衬底412将倾向于向内推挤且整个组合件将呈微笑状弯曲。
另外，温度可影响作用层414及衬底412中的应力。举例来说，随着温度升高，不同材料可以不同速率膨胀。如果作用层414以比衬底412快的速率膨胀，则衬底412可能归因于缺乏机械强度而翘曲。翘曲可能损坏作用层414中的装置，或稍后在制造中引起若干问题。
另外，作用层414中的组件经设计以在特定应力范围中适当地起作用。举例来说，作用层414中的张应力改善了nFET装置中的载流子移动力。
除了作用层414中的逐步形成的应力外，制造过程还损坏衬底412的前侧413。损坏是由等离子工艺(例如，反应性离子蚀刻及金属沉积)期间高能粒子对衬底412的冲击而引起。损坏还可由暴露到湿式蚀刻或清洗期间所使用的化学物质而引起。当衬底412的前侧413受损坏时，受损坏部分的应力与衬底412的主体的应力不同。应力的这些差异导致制造中的额外翘曲问题。
图5为说明常规堆叠式IC制造的流程图。在框515中，将晶片附接到载体晶片。所述载体晶片在制造期间为晶片提供支撑。在框520中，使所述晶片薄化以暴露穿硅通孔。在框525中，对晶片进行处理。示范性处理包括作用层的沉积、制造晶体管触点及制造晶体管互连件。在使晶片薄化及沉积作用层之后，翘曲可能归因于晶片中的不平衡应力而发生。载体晶片提供额外支撑以防止薄化之后的翘曲。在框530中，从所述晶片拆离载体晶片。拆离载体晶片包括溶解粘合剂及从晶片清洗掉粘合剂残余物。所述残余物难以完全移除，且清洗使用可能损坏晶片的苛性化学物质。
在框535中，将晶片分割成个别第一层裸片。在框540中，将第一层裸片附接到衬底面板。在框545中，将第二层裸片附接于所述第一层裸片上。在框550中，将第一层裸片、第二层裸片及衬底面板模制在一起。可在框550之后完成包括标记及附接封装连接件(例如，球状栅格)的额外制造。以下参看图6更详细地解释常规堆叠式IC制造。
图6A到图6K为说明常规堆叠式IC制造的框图。图6A包括具有穿硅通孔612及封装连接件611的晶片610。在图6B中，晶片610附接于载体晶片616上。载体晶片616在薄化及后续制造过程期间为晶片610提供额外支撑。如果不提供支撑，则晶片610可能会如以上参看图4所描述而翘曲。载体晶片616消耗并非最终产品的一部分的额外材料及资源。因此，载体晶片616增加了制造成本，但不提供最终产品的有形效益。另外，载体晶片616可稍后在制造中被移除，从而增加制造的时间长度。在附接到载体晶片616之后，可使晶片610在翘曲的可能性得以减小的情况下薄化。
参看图6C，使晶片610薄化以暴露穿硅通孔612。在图6D中，将隔离层626沉积于晶片610上。在图6E中，蚀刻隔离层626且将导电层631沉积于隔离层626的经蚀刻区中。在图6F中，将封装连接件636耦合到导电层631。在图6G中，拆离载体晶片616。接着在图6H中将晶片610分割成例如裸片646及裸片647的多个裸片。如图6I中所展示，裸片646、647中的每一者经由封装连接件611附接到衬底面板651上。衬底面板651还可含有互连件652。在图6J中，第二层裸片656附接于裸片646上且经由封装连接件636耦合。第二层裸片656的高度大于裸片646。因此，当第二层裸片656附接于裸片646上时，存在由于晶片621所经受的大的力而损坏晶片621的可能性。在第二层裸片656附接于裸片646上之后，在图6K中将第二层裸片656囊封于模制化合物661中。
在制造期间在使晶片薄化之前将所述晶片附接到衬底面板而非载体晶片提供了机械支撑，以防止由不平衡应力引起的处置期间的损坏或晶片翘曲。不同于载体晶片，衬底面板为产品的一部分且将不被移除。从制造中免除载体晶片及其它不必要材料(例如，粘合剂及清洗溶液)减小了成本及复杂性。
图7为说明根据一个实施例的用于制造IC的示范性工艺的流程图。在框720中，分割晶片以形成第一层裸片。在框725中，将第一层裸片附接到衬底面板。与产生最终产品中所使用的具有大厚度的半导体裸片相比，所述衬底面板以较低成本为半导体裸片提供支撑。在一个实施例中，在附接衬底面板之前使晶片薄化。在框730中，将第一层裸片及衬底面板囊封于模制化合物中。将所述模制化合物涂覆到电子零件及组合件，以提供支撑及保护。模制化合物可为含有环氧树脂、填充剂及添加剂的化合物。添加所述填充剂及添加剂以调整(例如)热膨胀系数。在框735中，使第一层裸片薄化。此操作可用以使晶片为进一步处理做好准备。举例来说，在堆叠式IC中，薄化暴露至少一个穿硅通孔。在框740中，在第一层裸片上完成包括封装连接件的沉积的额外制造。
如果需要单层IC，则制造流程图700可在框740之后结束。或者，如以下所描述，可使用额外制造以在第一层裸片上堆叠第二层裸片或其它裸片。所述单层IC可包括穿硅通孔或可不包括穿硅通孔。
在框745中，将第二层裸片附接于第一层裸片上。在框750中，将第二层裸片、第一层裸片及衬底面板囊封于模制化合物中。以下将参看图8呈现制造堆叠式IC的示范性工艺的特定实施例的细节。
图8为说明根据一个实施例的堆叠式IC的示范性制造的流程图。在框815中，可视情况(例如)通过背面研磨或蚀刻使晶片薄化。在附接到衬底面板之前薄化有助于模制化合物的均匀背面研磨。根据一个实施例，使晶片薄化到大约100μm。在堆叠式IC制造之前，所述晶片可为50μm到300μm。在框820中，将晶片分割成多个第一层裸片。分割可通过(例如)用金刚石划片器划片、用金刚石锯片器锯片或用激光切割来实现。
在框825中，将第一层裸片附接到衬底面板。举例来说，所述衬底面板可为纤维加强型树脂、有机膜或半导体。衬底面板为最终堆叠式IC产品的一部分。因此，衬底面板为第一层裸片提供支撑而稍后在制造中无需被移除。
在框830中，将第一层裸片及衬底面板囊封于模制化合物中。除了由衬底面板提供的支撑外，所述模制化合物还为第一层裸片提供额外支撑。在框835中，进一步的背面研磨使第一层裸片薄化，以暴露穿硅通孔。根据一个实施例，在进一步的背面研磨之后，第一层裸片的高度可小于50μm。可使用硅凹槽蚀刻来进一步使第一层裸片薄化。
在框840中，将隔离层沉积于第一层裸片上。举例来说，所述隔离层可为氮化硅、氧化硅或聚合物。在框845中，图案化所述隔离层且将导电层沉积于经蚀刻的区中。隔离层的图案化可(例如)通过以下步骤来实现：沉积光致抗蚀剂材料、经由光刻工具中的掩模来暴露所述光致抗蚀剂、蚀刻隔离层，及移除光致抗蚀剂材料。沉积于隔离层的经蚀刻的区中的金属层可(例如)耦合到第一层裸片中的穿硅通孔。所述导电层可为铜、铝，或铜、铝及其它元素的合金。
在框850中，将微凸块沉积于第一层裸片上。举例来说，微凸块的沉积可通过接种、执行凸块下金属化(UBM)、图案化及金属电镀而实现。所述微凸块可用于耦合到第二层裸片。在框855中，将第二层裸片附接于第一层裸片上且经由微凸块耦合。所述第二层裸片可为与第一层裸片相同类型的裸片，或在一个实施例中可为一互补裸片。举例来说，第二层裸片中的存储器装置可与第一层裸片中的逻辑单元互补。在框860中，将第一层裸片、第二层裸片及衬底面板囊封于模制化合物中。
图9A到图9L为说明根据一个实施例的示范性堆叠式IC制造过程的框图。晶片910包括封装连接件911及穿硅通孔912。在一个实例中，晶片910具有50μm到300μm的厚度。经由背面研磨使晶片910薄化以形成图9B中的晶片915。在一个实例中，晶片915的厚度可为100μm。晶片915经分割以形成图9C的第一层裸片921及第一层裸片922。
在图9D中，第一层裸片921、922附接到具有互连件927的衬底面板926。根据一个实施例，衬底面板926可为(例如)纤维加强型树脂或有机膜。与产生最终产品中所使用的具有大厚度的半导体晶片相比，衬底面板926以较低成本为半导体晶片提供支撑。
在图9E中，将模制化合物931置放于第一层裸片921、922周围，以将第一层裸片921、922固定于衬底面板926上。在一个实施例中，模制化合物931是通过将模制化合物置放于一模套中及接着将模制化合物沉积于第一层裸片921、922周围而形成。为了减少制造成本，最少量的模制化合物覆盖第一层裸片921、922。涂覆到第一层裸片921、922的额外模制化合物应经由背面研磨来移除。
在图9F中，经由背面研磨或凹槽蚀刻使第一层裸片921、922及模制化合物931薄化，以暴露穿硅通孔912。在一个实例中，厚度小于50μm。在图9G中，将隔离层941沉积于第一层裸片921、922上。在图9H中，使用光刻及蚀刻来图案化隔离层941，且将金属连接件946沉积于经蚀刻的区中。由于在执行任何后段工艺(BEOL)处理之前涂覆模制化合物931，因此隔离层941及其它BEOL层(未图示)与衬底面板926共面。
在图9I中，沉积微凸块951及其它封装连接件。在图9J中，第二层裸片952附接于第一层裸片921上，且第二层裸片953附接于第一层裸片922上。在图9K中，将模制化合物961置放于第二层裸片952、953上以固定第二层裸片952、953。
在模制化合物961凝固之后，可将第二层裸片952、953单一化为个别堆叠式IC。图9L为说明从晶片单一化的堆叠式IC的框图。
以上所描述的诸图说明若干工艺且未必按规定比例绘制。以上所描述的工艺可适用于制造任何大小的装置。
在制造期间利用衬底面板作为对晶片的支撑件的裸片的示范性制造减小了薄晶片的翘曲及处置风险。所述示范性制造还免除对载体晶片及用以附接所述载体晶片的相关联粘合剂的使用。所述制造进一步减小与附接第二层或额外层相关联的风险，第二层或额外层的附接与将厚裸片附接于薄裸片上相关联。所述示范性制造过程可应用于堆叠式IC。如以上所描述，所述制造过程充分利用现有制造技术，以允许容易地从2D IC转变到3D IC。
尽管术语“穿硅通孔”包括字“硅”，但应注意，未必以硅来建构穿硅通孔。实情为，所述材料可为任何装置衬底材料。
尽管已详细地描述了本发明及其优点，但应理解，在不脱离如由所附权利要求书所界定的本发明的技术的情况下，可在本文中进行各种改变、替代及变更。此外，本申请案的范围并不既定限于本说明书中所描述的过程、机器、制造、物质组成、手段、方法及步骤的特定实施例。如一般所属领域的技术人员将易于从本发明了解，可根据本发明利用目前现存或稍后待开发的执行与本文中所描述的相应实施例实质上相同的功能或实现与所述相应实施例实质上相同的结果的过程、机器、制造、物质组成、手段、方法或步骤。因此，所附权利要求书既定在其范围内包括这些过程、机器、制造、物质组成、手段、方法或步骤。

Claims (18)

1.一种半导体制造方法，所述方法包含：
将第一裸片附接到衬底面板；
在将所述第一裸片附接到所述衬底面板之后，将模制化合物涂覆到所述第一裸片及所述衬底面板；及
在涂覆所述模制化合物之后使所述第一裸片及所述模制化合物薄化。
2.根据权利要求1所述的方法，其进一步包含在将所述第一裸片附接到所述衬底面板之前使所述第一裸片薄化。
3.根据权利要求1所述的方法，其中使所述第一裸片薄化暴露至少一个穿硅通孔。
4.根据权利要求3所述的方法，其进一步包含在薄化之后进行以下步骤：
将隔离层沉积于所述第一裸片上；
在所述隔离层中图案化互连件；及
将封装连接件沉积于所述第一裸片上。
5.根据权利要求4所述的方法，其进一步包含将所述封装连接件耦合到所述第一裸片中的所述至少一个穿硅通孔。
6.根据权利要求5所述的方法，其进一步包含将第二裸片附接到所述封装连接件。
7.根据权利要求6所述的方法，其进一步包含将第二模制化合物涂覆到所述第二裸片。
8.根据权利要求1所述的方法，其进一步包含在将所述第一裸片附接到所述衬底面板之前将晶片分割成所述第一裸片。
9.根据权利要求1所述的方法，其进一步包含将所述第一裸片并入选自由以下各者组成的群组的装置中：音乐播放器、视频播放器、娱乐单元、导航装置、通信装置、个人数字助理PDA、固定位置数据单元，及计算机。
10.根据权利要求1所述的方法，其中涂覆所述模制化合物包含涂覆环氧树脂基模制化合物。
11.根据权利要求1所述的方法，其中涂覆所述模制化合物包括用模制化合物填充模套且将所述模套施加到所述第一裸片。
12.一种半导体制造方法，所述方法包含：
将晶片分割成第一层裸片；
将所述第一层裸片附接到衬底面板；
将第一模制化合物涂覆到所述第一层裸片及所述衬底面板；
背面研磨所述第一层裸片及所述第一模制化合物；
将第二层裸片附接到所述第一层裸片；及
将第二模制化合物涂覆到所述第一层裸片及所述第二层裸片。
13.根据权利要求12所述的方法，其进一步包含在分割所述晶片之前背面研磨所述晶片。
14.一种半导体装置，其包含：
衬底面板；
第一裸片，其附接于所述衬底面板上；及
模制化合物，其部分地环绕所述第一裸片且与所述衬底面板齐平。
15.根据权利要求14所述的半导体装置，其进一步包含耦合到所述第一裸片的第二裸片。
16.根据权利要求15所述的半导体装置，其进一步包含部分地环绕所述第二裸片的第二模制化合物。
17.根据权利要求14所述的半导体装置，其进一步包含经沉积而与所述模制化合物及所述第一裸片齐平的层。
18.一种半导体装置，其包含：
集成电路裸片；
用于将用于电子处理的装置固定于适当位置的装置；及
用于封装所述用于电子处理的装置的装置，其与所述用于固定的装置及所述用于电子处理的装置齐平。
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US20100283160A1 (en) 2010-11-11
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