KR100904771B1 - 3차원 집적회로 구조 및 제작 방법 - Google Patents

3차원 집적회로 구조 및 제작 방법 Download PDF

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Publication number
KR100904771B1
KR100904771B1 KR1020030047515A KR20030047515A KR100904771B1 KR 100904771 B1 KR100904771 B1 KR 100904771B1 KR 1020030047515 A KR1020030047515 A KR 1020030047515A KR 20030047515 A KR20030047515 A KR 20030047515A KR 100904771 B1 KR100904771 B1 KR 100904771B1
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KR
South Korea
Prior art keywords
single crystal
integrated circuit
layer
crystal semiconductor
semiconductor integrated
Prior art date
Application number
KR1020030047515A
Other languages
English (en)
Korean (ko)
Other versions
KR20050003326A (ko
Inventor
이상윤
Original Assignee
이상윤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 이상윤 filed Critical 이상윤
Priority to US10/873,969 priority Critical patent/US7052941B2/en
Priority to PCT/US2004/020122 priority patent/WO2005010934A2/en
Priority to CN2004800173344A priority patent/CN1809914B/zh
Priority to JP2006517574A priority patent/JP5202842B2/ja
Priority to EP04776960.9A priority patent/EP1636831B1/en
Publication of KR20050003326A publication Critical patent/KR20050003326A/ko
Priority to US11/378,059 priority patent/US20060275962A1/en
Priority to US11/606,523 priority patent/US7888764B2/en
Priority to US12/040,642 priority patent/US7800199B2/en
Priority to US12/345,503 priority patent/US7632738B2/en
Priority to US12/397,309 priority patent/US7863748B2/en
Priority to US12/470,344 priority patent/US8058142B2/en
Priority to US12/475,294 priority patent/US7799675B2/en
Application granted granted Critical
Publication of KR100904771B1 publication Critical patent/KR100904771B1/ko
Priority to US12/581,722 priority patent/US8471263B2/en
Priority to US12/618,542 priority patent/US7867822B2/en
Priority to US12/637,559 priority patent/US20100133695A1/en
Priority to US12/731,087 priority patent/US20100190334A1/en
Priority to US12/874,866 priority patent/US8071438B2/en
Priority to JP2011218346A priority patent/JP5294517B2/ja
Priority to JP2012135533A priority patent/JP2012253358A/ja

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Physics & Mathematics (AREA)
  • Thin Film Transistor (AREA)
  • Bipolar Transistors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Hall/Mr Elements (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Non-Volatile Memory (AREA)
KR1020030047515A 1996-11-04 2003-07-12 3차원 집적회로 구조 및 제작 방법 KR100904771B1 (ko)

Priority Applications (19)

Application Number Priority Date Filing Date Title
US10/873,969 US7052941B2 (en) 2003-06-24 2004-06-21 Method for making a three-dimensional integrated circuit structure
PCT/US2004/020122 WO2005010934A2 (en) 2003-06-24 2004-06-23 Three-dimensional integrated circuit structure and method of making same
CN2004800173344A CN1809914B (zh) 2003-06-24 2004-06-23 形成半导体结构的方法
JP2006517574A JP5202842B2 (ja) 2003-06-24 2004-06-23 三次元集積回路構造及びこれを作る方法
EP04776960.9A EP1636831B1 (en) 2003-06-24 2004-06-23 Method of making a three-dimensional integrated circuit structure
US11/378,059 US20060275962A1 (en) 2003-06-24 2006-03-17 Three-dimensional integrated circuit structure and method of making same
US11/606,523 US7888764B2 (en) 2003-06-24 2006-11-30 Three-dimensional integrated circuit structure
US12/040,642 US7800199B2 (en) 2003-06-24 2008-02-29 Semiconductor circuit
US12/345,503 US7632738B2 (en) 2003-06-24 2008-12-29 Wafer bonding method
US12/397,309 US7863748B2 (en) 2003-06-24 2009-03-03 Semiconductor circuit and method of fabricating the same
US12/470,344 US8058142B2 (en) 1996-11-04 2009-05-21 Bonded semiconductor structure and method of making the same
US12/475,294 US7799675B2 (en) 2003-06-24 2009-05-29 Bonded semiconductor structure and method of fabricating the same
US12/581,722 US8471263B2 (en) 2003-06-24 2009-10-19 Information storage system which includes a bonded semiconductor structure
US12/618,542 US7867822B2 (en) 2003-06-24 2009-11-13 Semiconductor memory device
US12/637,559 US20100133695A1 (en) 2003-01-12 2009-12-14 Electronic circuit with embedded memory
US12/731,087 US20100190334A1 (en) 2003-06-24 2010-03-24 Three-dimensional semiconductor structure and method of manufacturing the same
US12/874,866 US8071438B2 (en) 2003-06-24 2010-09-02 Semiconductor circuit
JP2011218346A JP5294517B2 (ja) 2003-06-24 2011-09-30 アッド‐オン層形成方法
JP2012135533A JP2012253358A (ja) 2003-06-24 2012-06-15 半導体構造

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020030040920 2003-06-24
KR20030040920 2003-06-24

Publications (2)

Publication Number Publication Date
KR20050003326A KR20050003326A (ko) 2005-01-10
KR100904771B1 true KR100904771B1 (ko) 2009-06-26

Family

ID=36840981

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020030047515A KR100904771B1 (ko) 1996-11-04 2003-07-12 3차원 집적회로 구조 및 제작 방법

Country Status (3)

Country Link
JP (2) JP5294517B2 (ja)
KR (1) KR100904771B1 (ja)
CN (1) CN1809914B (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110349961A (zh) * 2018-04-04 2019-10-18 三星电子株式会社 三维半导体存储器件及其制造方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100989546B1 (ko) * 2008-05-21 2010-10-25 이상윤 3차원 반도체 장치의 제조 방법
KR100975332B1 (ko) * 2008-05-30 2010-08-12 이상윤 반도체 장치 및 그 제조 방법
KR100791071B1 (ko) 2006-07-04 2008-01-02 삼성전자주식회사 일회 프로그래머블 소자, 이를 구비하는 전자시스템 및 그동작 방법
KR101468595B1 (ko) * 2008-12-19 2014-12-04 삼성전자주식회사 비휘발성 메모리 소자 및 그 제조 방법
US8395191B2 (en) * 2009-10-12 2013-03-12 Monolithic 3D Inc. Semiconductor device and structure
KR101669244B1 (ko) 2010-06-08 2016-10-25 삼성전자주식회사 에스램 소자 및 그 제조방법
KR101360947B1 (ko) * 2011-10-27 2014-02-10 윤재만 반도체 메모리 장치
JP2013161878A (ja) * 2012-02-02 2013-08-19 Renesas Electronics Corp 半導体装置、および半導体装置の製造方法
JP6128787B2 (ja) 2012-09-28 2017-05-17 キヤノン株式会社 半導体装置
US9112047B2 (en) * 2013-02-28 2015-08-18 Freescale Semiconductor, Inc. Split gate non-volatile memory (NVM) cell and method therefor
US9123546B2 (en) * 2013-11-14 2015-09-01 Taiwan Semiconductor Manufacturing Company Limited Multi-layer semiconductor device structures with different channel materials
CN104752393B (zh) * 2013-12-27 2017-11-03 中芯国际集成电路制造(上海)有限公司 Mos管电容器的布线结构及布线方法
US20150348874A1 (en) * 2014-05-29 2015-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC Interconnect Devices and Methods of Forming Same
WO2015195082A1 (en) 2014-06-16 2015-12-23 Intel Corporation Method for direct integration of memory die to logic die without use of through silicon vias (tsv)
WO2015195084A1 (en) * 2014-06-16 2015-12-23 Intel Corporation Embedded memory in interconnect stack on silicon die
US9893278B1 (en) * 2016-08-08 2018-02-13 Taiwan Semiconductor Manufacturing Co., Ltd. Embedded memory device between noncontigous interconnect metal layers
JP2018026518A (ja) * 2016-08-12 2018-02-15 東芝メモリ株式会社 半導体記憶装置
CN110785843A (zh) * 2017-08-31 2020-02-11 美光科技公司 具有带有两个晶体管及一个电容器的存储器单元且具有与参考电压耦合的晶体管的主体区的设备
US10930595B2 (en) 2017-09-28 2021-02-23 Taiwan Semiconductor Manufacturing Co., Ltd. Standard cells having via rail and deep via structures
US11374003B2 (en) * 2019-04-12 2022-06-28 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit
US11049880B2 (en) * 2019-08-02 2021-06-29 Sandisk Technologies Llc Three-dimensional memory device containing epitaxial ferroelectric memory elements and methods for forming the same
CN112635461B (zh) * 2020-12-08 2024-04-16 中国科学院微电子研究所 一种三维存算电路结构及其制备方法
CN113725301B (zh) * 2021-08-31 2024-07-02 上海积塔半导体有限公司 垂直型存储器件及其制备方法
CN114709168A (zh) * 2022-03-10 2022-07-05 长鑫存储技术有限公司 半导体结构及其制备方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5422302A (en) 1986-06-30 1995-06-06 Canon Kk Method for producing a three-dimensional semiconductor device
US5563084A (en) 1994-09-22 1996-10-08 Fraunhofer-Gesellschaft zur F orderung der angewandten Forschung e.V. Method of making a three-dimensional integrated circuit

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US4400715A (en) * 1980-11-19 1983-08-23 International Business Machines Corporation Thin film semiconductor device and method for manufacture
JPH04192368A (ja) * 1990-11-23 1992-07-10 Sony Corp 縦チャンネルｆｅｔ
US6194290B1 (en) * 1998-03-09 2001-02-27 Intersil Corporation Methods for making semiconductor devices by low temperature direct bonding
JP2003514399A (ja) * 1999-11-15 2003-04-15 インフィネオン テクノロジーズ アクチエンゲゼルシャフト 少なくとも１つのコンデンサおよびそれに接続された少なくとも１つのトランジスタを有する回路構造
JP2001250913A (ja) * 1999-12-28 2001-09-14 Mitsumasa Koyanagi ３次元半導体集積回路装置及びその製造方法
JP3735855B2 (ja) * 2000-02-17 2006-01-18 日本電気株式会社 半導体集積回路装置およびその駆動方法

Patent Citations (2)

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Publication number Priority date Publication date Assignee Title
US5422302A (en) 1986-06-30 1995-06-06 Canon Kk Method for producing a three-dimensional semiconductor device
US5563084A (en) 1994-09-22 1996-10-08 Fraunhofer-Gesellschaft zur F orderung der angewandten Forschung e.V. Method of making a three-dimensional integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110349961A (zh) * 2018-04-04 2019-10-18 三星电子株式会社 三维半导体存储器件及其制造方法

Also Published As

Publication number Publication date
CN1809914B (zh) 2010-06-09
JP5294517B2 (ja) 2013-09-18
JP2012064950A (ja) 2012-03-29
CN1809914A (zh) 2006-07-26
KR20050003326A (ko) 2005-01-10
JP2012253358A (ja) 2012-12-20

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