KR100737200B1 - 반도체 집적 회로 장치 - Google Patents

반도체 집적 회로 장치 Download PDF

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Publication number
KR100737200B1
KR100737200B1 KR1020010003400A KR20010003400A KR100737200B1 KR 100737200 B1 KR100737200 B1 KR 100737200B1 KR 1020010003400 A KR1020010003400 A KR 1020010003400A KR 20010003400 A KR20010003400 A KR 20010003400A KR 100737200 B1 KR100737200 B1 KR 100737200B1
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South Korea
Prior art keywords
insulating film
film
delete delete
sidewall insulating
conductor
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Expired - Lifetime
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KR1020010003400A
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English (en)
Korean (ko)
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KR20010076421A (ko
Inventor
사또루 야마다
기요노리 오유
다까후미 도꾸나가
히로유끼 에노모또
도시히로 세끼구찌
Original Assignee
엘피다 메모리, 아이엔씨.
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First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=18541062&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=KR100737200(B1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by 엘피다 메모리, 아이엔씨. filed Critical 엘피다 메모리, 아이엔씨.
Publication of KR20010076421A publication Critical patent/KR20010076421A/ko
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Publication of KR100737200B1 publication Critical patent/KR100737200B1/ko
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H10D1/716—Electrodes having non-planar surfaces, e.g. formed by texturisation having vertical extensions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/906—Dram with capacitor electrodes used for accessing, e.g. bit line is capacitor plate

Landscapes

  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
KR1020010003400A 2000-01-21 2001-01-20 반도체 집적 회로 장치 Expired - Lifetime KR100737200B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000-013476 2000-01-21
JP2000013476A JP3645463B2 (ja) 2000-01-21 2000-01-21 半導体集積回路装置

Publications (2)

Publication Number Publication Date
KR20010076421A KR20010076421A (ko) 2001-08-11
KR100737200B1 true KR100737200B1 (ko) 2007-07-10

Family

ID=18541062

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020010003400A Expired - Lifetime KR100737200B1 (ko) 2000-01-21 2001-01-20 반도체 집적 회로 장치

Country Status (4)

Country Link
US (2) US6555861B2 (enExample)
JP (1) JP3645463B2 (enExample)
KR (1) KR100737200B1 (enExample)
TW (1) TW508757B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101777005B1 (ko) * 2015-04-30 2017-09-08 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 게이트 상의 버퍼층 및 그 형성 방법

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002217383A (ja) * 2001-01-12 2002-08-02 Hitachi Ltd 半導体集積回路装置の製造方法および半導体集積回路装置
JP4528504B2 (ja) * 2003-08-22 2010-08-18 ルネサスエレクトロニクス株式会社 半導体装置とその製造方法
KR100809597B1 (ko) * 2006-04-06 2008-03-04 삼성전자주식회사 미세 패턴 형성 방법 및 이를 이용한 반도체 메모리 장치의형성 방법
JP2008021809A (ja) * 2006-07-12 2008-01-31 Elpida Memory Inc 半導体装置およびその製造方法
KR100891329B1 (ko) * 2007-01-26 2009-03-31 삼성전자주식회사 반도체 소자 및 그 제조 방법
JP2010287853A (ja) * 2009-06-15 2010-12-24 Elpida Memory Inc 半導体装置及びその製造方法
US8487369B2 (en) * 2009-10-30 2013-07-16 Hynix Semiconductor Inc. Semiconductor device with buried gates and buried bit lines and method for fabricating the same
JP2011216526A (ja) * 2010-03-31 2011-10-27 Renesas Electronics Corp 半導体装置の製造方法、及び半導体装置
JP2012134395A (ja) * 2010-12-22 2012-07-12 Elpida Memory Inc 半導体装置および半導体装置の製造方法
CN116133436A (zh) * 2021-11-12 2023-05-16 联华电子股份有限公司 半导体元件及其制作方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09219517A (ja) * 1995-12-08 1997-08-19 Sony Corp 半導体装置及びその製造方法
JPH1027906A (ja) * 1996-07-09 1998-01-27 Nippon Steel Corp 半導体装置の製造方法
JPH1032245A (ja) * 1996-07-17 1998-02-03 Toshiba Corp 半導体装置の製造方法
JPH11354749A (ja) * 1998-06-12 1999-12-24 Hitachi Ltd 半導体集積回路装置およびその製造方法
US20010024870A1 (en) * 1997-05-30 2001-09-27 Yoshikazu Tanabe Fabrication process of a semiconductor integrated circuit device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07106437A (ja) 1993-10-01 1995-04-21 Hitachi Ltd 半導体記憶装置
JP3203118B2 (ja) 1993-12-27 2001-08-27 三洋電機株式会社 非水電解液二次電池
JPH08204144A (ja) 1995-01-24 1996-08-09 Hitachi Ltd 半導体集積回路装置およびその製造方法
JP3869089B2 (ja) * 1996-11-14 2007-01-17 株式会社日立製作所 半導体集積回路装置の製造方法
JP2000013476A (ja) 1998-06-24 2000-01-14 Matsushita Electric Ind Co Ltd 電話装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09219517A (ja) * 1995-12-08 1997-08-19 Sony Corp 半導体装置及びその製造方法
JPH1027906A (ja) * 1996-07-09 1998-01-27 Nippon Steel Corp 半導体装置の製造方法
JPH1032245A (ja) * 1996-07-17 1998-02-03 Toshiba Corp 半導体装置の製造方法
US20010024870A1 (en) * 1997-05-30 2001-09-27 Yoshikazu Tanabe Fabrication process of a semiconductor integrated circuit device
JPH11354749A (ja) * 1998-06-12 1999-12-24 Hitachi Ltd 半導体集積回路装置およびその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101777005B1 (ko) * 2015-04-30 2017-09-08 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 게이트 상의 버퍼층 및 그 형성 방법

Also Published As

Publication number Publication date
US6555861B2 (en) 2003-04-29
US20030183941A1 (en) 2003-10-02
JP3645463B2 (ja) 2005-05-11
TW508757B (en) 2002-11-01
US20020043680A1 (en) 2002-04-18
US6791137B2 (en) 2004-09-14
KR20010076421A (ko) 2001-08-11
JP2001203337A (ja) 2001-07-27

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