KR100715260B1 - 반도체 집적회로장치의 제조방법 - Google Patents

반도체 집적회로장치의 제조방법 Download PDF

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KR100715260B1
KR100715260B1 KR1019990035596A KR19990035596A KR100715260B1 KR 100715260 B1 KR100715260 B1 KR 100715260B1 KR 1019990035596 A KR1019990035596 A KR 1019990035596A KR 19990035596 A KR19990035596 A KR 19990035596A KR 100715260 B1 KR100715260 B1 KR 100715260B1
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Prior art keywords
film
insulating film
forming
conductor
semiconductor substrate
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Expired - Fee Related
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KR1019990035596A
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Korean (ko)
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KR20000017559A (ko
Inventor
사이토마사요시
요시다마코토
카와카미히로시
우메자와타다시
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엘피다 메모리 가부시키가이샤
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Publication of KR20000017559A publication Critical patent/KR20000017559A/ko
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)
KR1019990035596A 1998-08-31 1999-08-26 반도체 집적회로장치의 제조방법 Expired - Fee Related KR100715260B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP98-246147 1998-08-31
JP10246147A JP2000077625A (ja) 1998-08-31 1998-08-31 半導体集積回路装置の製造方法

Publications (2)

Publication Number Publication Date
KR20000017559A KR20000017559A (ko) 2000-03-25
KR100715260B1 true KR100715260B1 (ko) 2007-05-07

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ID=17144195

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KR1019990035596A Expired - Fee Related KR100715260B1 (ko) 1998-08-31 1999-08-26 반도체 집적회로장치의 제조방법

Country Status (6)

Country Link
US (1) US6235620B1 (enExample)
JP (1) JP2000077625A (enExample)
KR (1) KR100715260B1 (enExample)
CN (1) CN1210783C (enExample)
SG (1) SG75976A1 (enExample)
TW (1) TW451460B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101912776B1 (ko) 2011-02-28 2018-10-29 도쿄엘렉트론가부시키가이샤 플라즈마 에칭 방법 및 반도체 장치의 제조 방법 그리고 컴퓨터 기억 매체

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US6159818A (en) * 1999-09-02 2000-12-12 Micron Technology, Inc. Method of forming a container capacitor structure
JP2001185552A (ja) * 1999-12-27 2001-07-06 Hitachi Ltd 半導体集積回路装置およびその製造方法
JP4142228B2 (ja) * 2000-02-01 2008-09-03 株式会社ルネサステクノロジ 半導体集積回路装置
KR100362834B1 (ko) 2000-05-02 2002-11-29 삼성전자 주식회사 반도체 장치의 산화막 형성 방법 및 이에 의하여 제조된 반도체 장치
US7053005B2 (en) * 2000-05-02 2006-05-30 Samsung Electronics Co., Ltd. Method of forming a silicon oxide layer in a semiconductor manufacturing process
US6683380B2 (en) 2000-07-07 2004-01-27 Texas Instruments Incorporated Integrated circuit with bonding layer over active circuitry
JP2002118167A (ja) 2000-10-06 2002-04-19 Nec Corp 半導体装置の製造方法
US6479405B2 (en) * 2000-10-12 2002-11-12 Samsung Electronics Co., Ltd. Method of forming silicon oxide layer in semiconductor manufacturing process using spin-on glass composition and isolation method using the same method
DE10120929A1 (de) * 2001-04-30 2002-10-31 Infineon Technologies Ag Herstellungsverfahren für eine integrierte Schaltung
FR2832854B1 (fr) * 2001-11-28 2004-03-12 St Microelectronics Sa Fabrication de memoire dram et de transistor mos
JP3612525B2 (ja) * 2002-06-04 2005-01-19 Ｎｅｃ液晶テクノロジー株式会社 薄膜半導体装置の製造方法及びそのレジストパターン形成方法
JP4018954B2 (ja) * 2002-08-20 2007-12-05 エルピーダメモリ株式会社 半導体装置の製造方法
US7037840B2 (en) * 2004-01-26 2006-05-02 Micron Technology, Inc. Methods of forming planarized surfaces over semiconductor substrates
US7507661B2 (en) * 2004-08-11 2009-03-24 Spansion Llc Method of forming narrowly spaced flash memory contact openings and lithography masks
US7605033B2 (en) 2004-09-01 2009-10-20 Micron Technology, Inc. Low resistance peripheral local interconnect contacts with selective wet strip of titanium
TWI242828B (en) * 2004-12-20 2005-11-01 Powerchip Semiconductor Corp Inspection method for an semiconductor device
JP5096669B2 (ja) 2005-07-06 2012-12-12 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法
KR100876957B1 (ko) * 2006-10-20 2009-01-07 삼성전자주식회사 노어형 불 휘발성 메모리 소자 및 이를 형성하기 위한 형성방법
JP2009054683A (ja) * 2007-08-24 2009-03-12 Panasonic Corp 半導体装置およびその製造方法
JP2010056156A (ja) * 2008-08-26 2010-03-11 Renesas Technology Corp 半導体装置およびその製造方法
US8373239B2 (en) 2010-06-08 2013-02-12 International Business Machines Corporation Structure and method for replacement gate MOSFET with self-aligned contact using sacrificial mandrel dielectric
JP2015153870A (ja) 2014-02-13 2015-08-24 キヤノン株式会社 半導体装置の製造方法、光電変換装置
US12193212B2 (en) * 2021-03-24 2025-01-07 Chanigxin Memory Technologies, Inc. Method of forming semiconductor device and semiconductor device
CN115843175B (zh) * 2021-08-20 2025-10-28 长鑫存储技术有限公司 半导体结构及其制备方法
EP4160664A1 (en) 2021-08-20 2023-04-05 Changxin Memory Technologies, Inc. Semiconductor structure and manufacturing method therefor

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KR980011858A (ko) * 1996-07-19 1998-04-30 문정환 반도체장치의 제조방법
KR19980025631A (ko) * 1996-10-04 1998-07-15 문정환 반도체 소자의 제조 방법

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US5482894A (en) * 1994-08-23 1996-01-09 Texas Instruments Incorporated Method of fabricating a self-aligned contact using organic dielectric materials
JP3571088B2 (ja) 1994-10-25 2004-09-29 沖電気工業株式会社 Ｄｒａｍセルコンタクトの構造及びその形成方法
KR0141950B1 (ko) * 1994-12-22 1998-06-01 문정환 반도체소자의 제조방법
JPH08316313A (ja) 1995-05-18 1996-11-29 Sony Corp コンタクトホールの形成方法
JP3402022B2 (ja) * 1995-11-07 2003-04-28 三菱電機株式会社 半導体装置の製造方法
US5795820A (en) * 1996-07-01 1998-08-18 Advanced Micro Devices Method for simplifying the manufacture of an interlayer dielectric stack
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JPH11186236A (ja) * 1997-12-24 1999-07-09 Mitsubishi Electric Corp エッチング方法
US6046103A (en) * 1999-08-02 2000-04-04 Taiwan Semiconductor Manufacturing Company Borderless contact process for a salicide devices

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KR980011858A (ko) * 1996-07-19 1998-04-30 문정환 반도체장치의 제조방법
KR19980025631A (ko) * 1996-10-04 1998-07-15 문정환 반도체 소자의 제조 방법

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101912776B1 (ko) 2011-02-28 2018-10-29 도쿄엘렉트론가부시키가이샤 플라즈마 에칭 방법 및 반도체 장치의 제조 방법 그리고 컴퓨터 기억 매체

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KR20000017559A (ko) 2000-03-25
CN1246727A (zh) 2000-03-08
JP2000077625A (ja) 2000-03-14
US6235620B1 (en) 2001-05-22
TW451460B (en) 2001-08-21
CN1210783C (zh) 2005-07-13
SG75976A1 (en) 2000-10-24

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