KR100689726B1 - 반도체 장치 - Google Patents
반도체 장치 Download PDFInfo
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- KR100689726B1 KR100689726B1 KR1020020002925A KR20020002925A KR100689726B1 KR 100689726 B1 KR100689726 B1 KR 100689726B1 KR 1020020002925 A KR1020020002925 A KR 1020020002925A KR 20020002925 A KR20020002925 A KR 20020002925A KR 100689726 B1 KR100689726 B1 KR 100689726B1
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Abstract
Description
Claims (3)
- 표면과 저면을 갖는 와이어본드 패드와,표면과 저면을 갖는 다이본드 패드로서, 그 다이본드 패드와 상기 와이어본드 패드 사이에 간격을 갖도록, 상기 와이어본드 패드에 대하여 실질적으로 평행하고, 또한 상기 와이어본드 패드로부터 종방향으로 배치된 다이본드 패드와,상기 다이본드 패드의 표면에 탑재된 반도체소자와,상기 반도체소자의 제1전극과 상기 와이어본드 패드의 표면을 전기적으로 접속하도록 형성된 와이어와,상기 와이어본드 패드와 상기 다이본드 패드의 저면만이 노출하도록, 상기 와이어본드 패드, 상기 다이본드 패드, 상기 반도체소자 및 상기 와이어를 봉지하고, 상기 다이본드 패드와 상기 와이어본드 패드 사이의 공간을 메우는 밀봉수지를 구비하고,상기 와이어본드 패드와 상기 다이본드 패드가 상기 종방향에 직교하는 횡방향의 폭치수를 갖고, 상기 횡방향의 폭치수가 반도체장치의 횡방향의 폭치수에 동일한 것을 특징으로 반도체장치.
- 제 1 항에 있어서,표면과 저면을 갖고, 상기 와이어본드 패드에 대하여 실질적으로 평행하게 배치된 제2와이어본드 패드와,상기 반도체소자의 제2전극과 상기 제2와이어본드 패드의 표면을 전기적으로 접속하도록 형성된 제2와이어를 구비하고,상기 다이본드 패드가 상기 와이어본드 패드와 상기 제2와이어본드 패드에 대하여 실질적으로 평행하고, 이들 와이어본드 패드 사이에 배치되어, 각각의 상기 다이본드 패드와, 상기 와이어본드 패드와 상기 제2와이어본드 패드의 양쪽 사이에 간격을 갖도록, 이들 와이어본드 패드로부터 종방향으로 배치되고,상기 밀봉수지가, 상기 와이어본드 패드, 상기 제2와이어본드 패드 및 상기 다이본드 패드의 저면만이 노출하도록, 상기 제2와이어본드 패드와 상기 제2와이어를 봉지하고, 또한 상기 다이본드 패드와, 상기 와이어본드 패드와 상기 제2와이어본드 패드의 양쪽 사이의 간격을 메우고,상기 제2와이어본드 패드가, 상기 종방향에 직교하는 횡방향의 폭치수를 갖고, 상기 횡방향의 폭치수가 반도체장치의 횡방향의 폭치수에 동일한 것을 특징을 하는 반도체장치.
- 제1반도체장치와 제2반도체장치를 포함한 반도체장치로서, 각각의 반도체장치는,표면과 저면을 갖는 와이어본드 패드와,표면과 저면을 갖는 다이본드 패드로서, 상기 다이본드 패드와 상기 와이어본드 사이에 간격을 갖도록, 상기 와이어본드 패드에 대하여 실질적으로 평행하고, 또한 상기 와이어본드 패드로부터 종방향에 배치된 상기 다이패드와,상기 다이본드 패드의 표면에 탑재된 반도체소자와,상기 반도체소자의 제1전극과 상기 와이어본드 패드의 표면을 전기적으로 접속하도록 구성된 와이어와,밀봉수지를 구비하고,상기 제1반도체장치와 상기 제2반도체장치가, 상기 제1반도체장치와 제2반도체장치 사이에 간격이 형성되도록, 종방향의 어레이로서 상기 종방향으로 배치되고,상기 밀봉수지가, 상기 제1반도체장치와 상기 제2반도체장치를 함께 몰드하고, 상기 제1반도체장치와 제2반도체장치 각각의 와이어본드 패드와 다이본드 패드의 저면만이 노출하도록, 상기 와이어본드 패드, 상기 다이본드 패드, 상기 반도체소자 및 와이어를 봉지하고, 상기 제1반도체장치와 제1반도체장치 각각의 상기 다이본드 패드와 상기 와이어본드 패드의 사이 공간을 메우도록 형성되며,상기 제1반도체장치와 제2반도체장치 각각의 상기 와이어본드 패드와 상기 다이본드 패드가, 상기 종방향으로 직교하는 횡방향의 폭치수를 갖고, 상기 횡방향의 폭치수가 반도체장치의 횡방향의 폭치수에 동일한 것을 특징으로 하는 반도체장치.
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JP12889698A JP3862410B2 (ja) | 1998-05-12 | 1998-05-12 | 半導体装置の製造方法及びその構造 |
JPJP-P-1998-00128896 | 1998-05-12 | ||
KR1019990007841A KR100345621B1 (ko) | 1998-05-12 | 1999-03-10 | 반도체 장치의 제조방법 및 그 방법에 사용되는 리드 프레임 |
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KR1020020002925A KR100689726B1 (ko) | 1998-05-12 | 2002-01-18 | 반도체 장치 |
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JP (1) | JP3862410B2 (ko) |
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Families Citing this family (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002110884A (ja) * | 2000-10-02 | 2002-04-12 | Nitto Denko Corp | リードフレーム積層物 |
AU2003261857A1 (en) * | 2003-08-29 | 2005-03-29 | Renesas Technology Corp. | Semiconductor device manufacturing method |
US7056766B2 (en) * | 2003-12-09 | 2006-06-06 | Freescale Semiconductor, Inc. | Method of forming land grid array packaged device |
US7462317B2 (en) | 2004-11-10 | 2008-12-09 | Enpirion, Inc. | Method of manufacturing an encapsulated package for a magnetic device |
US7426780B2 (en) | 2004-11-10 | 2008-09-23 | Enpirion, Inc. | Method of manufacturing a power module |
US8139362B2 (en) * | 2005-10-05 | 2012-03-20 | Enpirion, Inc. | Power module with a magnetic device having a conductive clip |
US8631560B2 (en) | 2005-10-05 | 2014-01-21 | Enpirion, Inc. | Method of forming a magnetic device having a conductive clip |
US8701272B2 (en) | 2005-10-05 | 2014-04-22 | Enpirion, Inc. | Method of forming a power module with a magnetic device having a conductive clip |
US7688172B2 (en) | 2005-10-05 | 2010-03-30 | Enpirion, Inc. | Magnetic device having a conductive clip |
US7952459B2 (en) | 2007-09-10 | 2011-05-31 | Enpirion, Inc. | Micromagnetic device and method of forming the same |
US7955868B2 (en) | 2007-09-10 | 2011-06-07 | Enpirion, Inc. | Method of forming a micromagnetic device |
US8133529B2 (en) | 2007-09-10 | 2012-03-13 | Enpirion, Inc. | Method of forming a micromagnetic device |
US7920042B2 (en) | 2007-09-10 | 2011-04-05 | Enpirion, Inc. | Micromagnetic device and method of forming the same |
US8018315B2 (en) | 2007-09-10 | 2011-09-13 | Enpirion, Inc. | Power converter employing a micromagnetic device |
US8686698B2 (en) | 2008-04-16 | 2014-04-01 | Enpirion, Inc. | Power converter with controller operable in selected modes of operation |
US9246390B2 (en) | 2008-04-16 | 2016-01-26 | Enpirion, Inc. | Power converter with controller operable in selected modes of operation |
US8692532B2 (en) | 2008-04-16 | 2014-04-08 | Enpirion, Inc. | Power converter with controller operable in selected modes of operation |
US8541991B2 (en) | 2008-04-16 | 2013-09-24 | Enpirion, Inc. | Power converter with controller operable in selected modes of operation |
US8266793B2 (en) | 2008-10-02 | 2012-09-18 | Enpirion, Inc. | Module having a stacked magnetic device and semiconductor device and method of forming the same |
US8339802B2 (en) | 2008-10-02 | 2012-12-25 | Enpirion, Inc. | Module having a stacked magnetic device and semiconductor device and method of forming the same |
US8153473B2 (en) | 2008-10-02 | 2012-04-10 | Empirion, Inc. | Module having a stacked passive element and method of forming the same |
US9054086B2 (en) | 2008-10-02 | 2015-06-09 | Enpirion, Inc. | Module having a stacked passive element and method of forming the same |
US9548714B2 (en) | 2008-12-29 | 2017-01-17 | Altera Corporation | Power converter with a dynamically configurable controller and output filter |
US8698463B2 (en) | 2008-12-29 | 2014-04-15 | Enpirion, Inc. | Power converter with a dynamically configurable controller based on a power conversion mode |
US8867295B2 (en) | 2010-12-17 | 2014-10-21 | Enpirion, Inc. | Power converter for a memory module |
JP5549612B2 (ja) * | 2011-01-31 | 2014-07-16 | 三菱電機株式会社 | 半導体装置の製造方法 |
WO2012120568A1 (ja) | 2011-03-09 | 2012-09-13 | パナソニック株式会社 | 半導体装置 |
US9509217B2 (en) | 2015-04-20 | 2016-11-29 | Altera Corporation | Asymmetric power flow controller for a power converter and method of operating the same |
JP6630390B2 (ja) * | 2018-03-29 | 2020-01-15 | アオイ電子株式会社 | 半導体装置 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0982741A (ja) * | 1995-09-19 | 1997-03-28 | Seiko Epson Corp | チップキャリアの構造およびその製造方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5636145A (en) | 1979-08-31 | 1981-04-09 | Hitachi Ltd | Thin semiconductor integrated circuit device and its manufacture |
JPH0783074B2 (ja) | 1985-12-06 | 1995-09-06 | ソニー株式会社 | モ−ルドトランジスタ |
JPH01145837A (ja) * | 1987-12-02 | 1989-06-07 | Toshiba Corp | 半導体装置 |
US5157475A (en) * | 1988-07-08 | 1992-10-20 | Oki Electric Industry Co., Ltd. | Semiconductor device having a particular conductive lead structure |
US5442228A (en) * | 1992-04-06 | 1995-08-15 | Motorola, Inc. | Monolithic shielded integrated circuit |
JPH0621305A (ja) | 1992-06-30 | 1994-01-28 | Matsushita Electron Corp | 半導体装置 |
KR100247908B1 (ko) * | 1992-12-30 | 2000-03-15 | 윤종용 | 반도체장치 |
JP2960283B2 (ja) * | 1993-06-14 | 1999-10-06 | 株式会社東芝 | 樹脂封止型半導体装置の製造方法と、この製造方法に用いられる複数の半導体素子を載置するためのリードフレームと、この製造方法によって製造される樹脂封止型半導体装置 |
US5977613A (en) * | 1996-03-07 | 1999-11-02 | Matsushita Electronics Corporation | Electronic component, method for making the same, and lead frame and mold assembly for use therein |
KR0185512B1 (ko) * | 1996-08-19 | 1999-03-20 | 김광호 | 칼럼리드구조를갖는패키지및그의제조방법 |
TW467401U (en) * | 1997-03-21 | 2001-12-01 | Rohm Co Ltd | Lead frame and the semiconductor device utilizing the lead frame |
US6025640A (en) * | 1997-07-16 | 2000-02-15 | Dai Nippon Insatsu Kabushiki Kaisha | Resin-sealed semiconductor device, circuit member for use therein and method of manufacturing resin-sealed semiconductor device |
MY118338A (en) * | 1998-01-26 | 2004-10-30 | Motorola Semiconductor Sdn Bhd | A leadframe, a method of manufacturing a leadframe and a method of packaging an electronic component utilising the leadframe. |
-
1998
- 1998-05-12 JP JP12889698A patent/JP3862410B2/ja not_active Expired - Lifetime
-
1999
- 1999-01-21 US US09/234,321 patent/US6252306B1/en not_active Expired - Lifetime
- 1999-02-04 TW TW088101674A patent/TW409375B/zh not_active IP Right Cessation
- 1999-03-10 KR KR1019990007841A patent/KR100345621B1/ko not_active IP Right Cessation
-
2001
- 2001-04-09 US US09/828,132 patent/US6372546B2/en not_active Expired - Lifetime
-
2002
- 2002-01-18 KR KR1020020002925A patent/KR100689726B1/ko not_active IP Right Cessation
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0982741A (ja) * | 1995-09-19 | 1997-03-28 | Seiko Epson Corp | チップキャリアの構造およびその製造方法 |
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KR19990087868A (ko) | 1999-12-27 |
US20010041384A1 (en) | 2001-11-15 |
KR20020033654A (ko) | 2002-05-07 |
US6372546B2 (en) | 2002-04-16 |
JP3862410B2 (ja) | 2006-12-27 |
JPH11330313A (ja) | 1999-11-30 |
US6252306B1 (en) | 2001-06-26 |
TW409375B (en) | 2000-10-21 |
KR100345621B1 (ko) | 2002-07-27 |
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