KR100425391B1 - 반도체 장치 및 그 제조 방법, 회로기판 및 전자기기 - Google Patents
반도체 장치 및 그 제조 방법, 회로기판 및 전자기기 Download PDFInfo
- Publication number
- KR100425391B1 KR100425391B1 KR10-2001-0002836A KR20010002836A KR100425391B1 KR 100425391 B1 KR100425391 B1 KR 100425391B1 KR 20010002836 A KR20010002836 A KR 20010002836A KR 100425391 B1 KR100425391 B1 KR 100425391B1
- Authority
- KR
- South Korea
- Prior art keywords
- hole
- semiconductor device
- conductive layer
- manufacturing
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
- H10P14/46—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a liquid
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
- H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
- H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
- H10W20/0238—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes through pads or through electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W20/211—Through-semiconductor vias, e.g. TSVs
- H10W20/212—Top-view shapes or dispositions, e.g. top-view layouts of the vias
- H10W20/2125—Top-view shapes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/65—Shapes or dispositions of interconnections
- H10W70/652—Cross-sectional shapes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/019—Manufacture or treatment of bond pads
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/241—Dispositions, e.g. layouts
- H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/921—Structures or relative sizes of bond pads
- H10W72/923—Bond pads having multiple stacked layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/934—Cross-sectional shape, i.e. in side view
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/941—Dispositions of bond pads
- H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/20—Configurations of stacked chips
- H10W90/291—Configurations of stacked chips characterised by containers, encapsulations, or other housings for the stacked chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/20—Configurations of stacked chips
- H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000012670A JP3736607B2 (ja) | 2000-01-21 | 2000-01-21 | 半導体装置及びその製造方法、回路基板並びに電子機器 |
| JP2000-12670 | 2000-01-21 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20010076331A KR20010076331A (ko) | 2001-08-11 |
| KR100425391B1 true KR100425391B1 (ko) | 2004-03-30 |
Family
ID=18540360
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-2001-0002836A Expired - Lifetime KR100425391B1 (ko) | 2000-01-21 | 2001-01-18 | 반도체 장치 및 그 제조 방법, 회로기판 및 전자기기 |
Country Status (4)
| Country | Link |
|---|---|
| US (2) | US6667551B2 (https=) |
| JP (1) | JP3736607B2 (https=) |
| KR (1) | KR100425391B1 (https=) |
| TW (1) | TW508789B (https=) |
Families Citing this family (98)
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|---|---|---|---|---|
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| US6630743B2 (en) * | 2001-02-27 | 2003-10-07 | International Business Machines Corporation | Copper plated PTH barrels and methods for fabricating |
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| JP3690380B2 (ja) * | 2002-08-02 | 2005-08-31 | セイコーエプソン株式会社 | 材料の配置方法、電子装置の製造方法、電気光学装置の製造方法 |
| US6867983B2 (en) * | 2002-08-07 | 2005-03-15 | Avery Dennison Corporation | Radio frequency identification device and method |
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| JP4072677B2 (ja) | 2003-01-15 | 2008-04-09 | セイコーエプソン株式会社 | 半導体チップ、半導体ウエハ、半導体装置及びその製造方法、回路基板並びに電子機器 |
| JP2004311948A (ja) * | 2003-03-27 | 2004-11-04 | Seiko Epson Corp | 半導体装置、半導体デバイス、電子機器、および半導体装置の製造方法 |
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| TW202247905A (zh) | 2021-04-29 | 2022-12-16 | 美商阿普托麥克股份有限公司 | 用於氣溶膠噴射裝置之高可靠性鞘護輸送路徑 |
| JP2024135267A (ja) * | 2023-03-22 | 2024-10-04 | 株式会社東芝 | 電子装置及びその製造方法 |
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- 2000-01-21 JP JP2000012670A patent/JP3736607B2/ja not_active Expired - Lifetime
-
2001
- 2001-01-18 TW TW090101162A patent/TW508789B/zh not_active IP Right Cessation
- 2001-01-18 KR KR10-2001-0002836A patent/KR100425391B1/ko not_active Expired - Lifetime
- 2001-01-22 US US09/765,433 patent/US6667551B2/en not_active Expired - Lifetime
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| JPS5326689A (en) * | 1976-08-25 | 1978-03-11 | Hitachi Ltd | Semiconductor integrated circuit unit |
| JPS5326666A (en) * | 1976-08-25 | 1978-03-11 | Hitachi Ltd | Semiconduct or device |
| JPS5837944A (ja) * | 1981-08-28 | 1983-03-05 | Fujitsu Ltd | 半導体チツプの実装構造 |
| JPS59222954A (ja) * | 1983-06-01 | 1984-12-14 | Hitachi Ltd | 積層半導体集積回路およびその製法 |
| JPH11204519A (ja) * | 1998-01-08 | 1999-07-30 | Matsushita Electron Corp | 半導体装置及びその製造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2001203316A (ja) | 2001-07-27 |
| JP3736607B2 (ja) | 2006-01-18 |
| US6667551B2 (en) | 2003-12-23 |
| US20010027011A1 (en) | 2001-10-04 |
| US20040092099A1 (en) | 2004-05-13 |
| US6852621B2 (en) | 2005-02-08 |
| KR20010076331A (ko) | 2001-08-11 |
| TW508789B (en) | 2002-11-01 |
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