KR100393425B1 - 반도체장치의 제조방법 - Google Patents

반도체장치의 제조방법 Download PDF

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Publication number
KR100393425B1
KR100393425B1 KR10-2000-0070418A KR20000070418A KR100393425B1 KR 100393425 B1 KR100393425 B1 KR 100393425B1 KR 20000070418 A KR20000070418 A KR 20000070418A KR 100393425 B1 KR100393425 B1 KR 100393425B1
Authority
KR
South Korea
Prior art keywords
semiconductor device
columnar electrode
columnar
manufacturing
electrode
Prior art date
Application number
KR10-2000-0070418A
Other languages
English (en)
Korean (ko)
Other versions
KR20010061956A (ko
Inventor
미하라이치로
Original Assignee
가시오게산키 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 가시오게산키 가부시키가이샤 filed Critical 가시오게산키 가부시키가이샤
Publication of KR20010061956A publication Critical patent/KR20010061956A/ko
Application granted granted Critical
Publication of KR100393425B1 publication Critical patent/KR100393425B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
KR10-2000-0070418A 1999-12-09 2000-11-24 반도체장치의 제조방법 KR100393425B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP35002199A JP3409759B2 (ja) 1999-12-09 1999-12-09 半導体装置の製造方法
JP99-350021 1999-12-09

Publications (2)

Publication Number Publication Date
KR20010061956A KR20010061956A (ko) 2001-07-07
KR100393425B1 true KR100393425B1 (ko) 2003-08-02

Family

ID=18407709

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2000-0070418A KR100393425B1 (ko) 1999-12-09 2000-11-24 반도체장치의 제조방법

Country Status (3)

Country Link
US (1) US6467674B1 (ja)
JP (1) JP3409759B2 (ja)
KR (1) KR100393425B1 (ja)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6642136B1 (en) 2001-09-17 2003-11-04 Megic Corporation Method of making a low fabrication cost, high performance, high reliability chip scale package
US8021976B2 (en) 2002-10-15 2011-09-20 Megica Corporation Method of wire bonding over active area of a semiconductor circuit
US6815324B2 (en) 2001-02-15 2004-11-09 Megic Corporation Reliable metal bumps on top of I/O pads after removal of test probe marks
US8158508B2 (en) 2001-03-05 2012-04-17 Megica Corporation Structure and manufacturing method of a chip scale package
TWI313507B (en) 2002-10-25 2009-08-11 Megica Corporatio Method for assembling chips
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US7099293B2 (en) * 2002-05-01 2006-08-29 Stmicroelectronics, Inc. Buffer-less de-skewing for symbol combination in a CDMA demodulator
TWI245402B (en) 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
JP3829325B2 (ja) * 2002-02-07 2006-10-04 日本電気株式会社 半導体素子およびその製造方法並びに半導体装置の製造方法
JP3888302B2 (ja) * 2002-12-24 2007-02-28 カシオ計算機株式会社 半導体装置
TWI239581B (en) * 2003-01-16 2005-09-11 Casio Computer Co Ltd Semiconductor device and method of manufacturing the same
WO2004109771A2 (en) 2003-06-03 2004-12-16 Casio Computer Co., Ltd. Stackable semiconductor device and method of manufacturing the same
JP3757971B2 (ja) * 2003-10-15 2006-03-22 カシオ計算機株式会社 半導体装置の製造方法
TWI278048B (en) 2003-11-10 2007-04-01 Casio Computer Co Ltd Semiconductor device and its manufacturing method
JP3925809B2 (ja) 2004-03-31 2007-06-06 カシオ計算機株式会社 半導体装置およびその製造方法
US8067837B2 (en) 2004-09-20 2011-11-29 Megica Corporation Metallization structure over passivation layer for IC chip
WO2006040419A1 (fr) * 2004-10-13 2006-04-20 Commissariat A L'energie Atomique Procede d'obtention de couches localisees sur un circuit hybride
JP4972280B2 (ja) * 2004-12-09 2012-07-11 ローム株式会社 半導体装置
US8294279B2 (en) 2005-01-25 2012-10-23 Megica Corporation Chip package with dam bar restricting flow of underfill
JP4949719B2 (ja) * 2006-04-07 2012-06-13 ラピスセミコンダクタ株式会社 半導体装置及びその製造方法
TWI462199B (zh) * 2010-12-21 2014-11-21 Chipmos Technologies Inc 凸塊結構及其製作方法
KR20130012470A (ko) * 2011-07-25 2013-02-04 삼성전기주식회사 범프 형성 방법, 및 상기 범프를 포함하는 기판

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0321021A (ja) * 1989-06-19 1991-01-29 Kyushu Electron Metal Co Ltd 半導体基板の面取り方法及びその装置
JP3057130B2 (ja) * 1993-02-18 2000-06-26 三菱電機株式会社 樹脂封止型半導体パッケージおよびその製造方法
FR2717308B1 (fr) * 1994-03-14 1996-07-26 Sgs Thomson Microelectronics Dispositif de protection contre des surtensions dans des circuits intégrés.
JP3449796B2 (ja) 1994-08-18 2003-09-22 ソニー株式会社 樹脂封止型半導体装置の製造方法
JP3552845B2 (ja) * 1996-04-25 2004-08-11 株式会社ルネサステクノロジ 半導体装置の製造方法
US5950102A (en) * 1997-02-03 1999-09-07 Industrial Technology Research Institute Method for fabricating air-insulated multilevel metal interconnections for integrated circuits
JP3767154B2 (ja) * 1997-06-17 2006-04-19 セイコーエプソン株式会社 電気光学装置用基板、電気光学装置、電子機器及び投写型表示装置
JP3328193B2 (ja) * 1998-07-08 2002-09-24 信越半導体株式会社 半導体ウエーハの製造方法
US6140155A (en) * 1998-12-24 2000-10-31 Casio Computer Co., Ltd. Method of manufacturing semiconductor device using dry photoresist film
US6319851B1 (en) * 1999-02-03 2001-11-20 Casio Computer Co., Ltd. Method for packaging semiconductor device having bump electrodes
JP3430289B2 (ja) * 1999-02-03 2003-07-28 カシオ計算機株式会社 半導体装置の製造方法
JP3405259B2 (ja) * 1999-03-17 2003-05-12 カシオ計算機株式会社 突起電極の形成方法及び突起電極を備えたフィルム基板の製造方法並びに突起電極を備えた半導体装置の製造方法
JP3496569B2 (ja) * 1999-04-23 2004-02-16 カシオ計算機株式会社 半導体装置及びその製造方法並びにその実装構造
JP3502800B2 (ja) * 1999-12-15 2004-03-02 新光電気工業株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
JP2001168128A (ja) 2001-06-22
US6467674B1 (en) 2002-10-22
JP3409759B2 (ja) 2003-05-26
KR20010061956A (ko) 2001-07-07

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