TWI431699B - 用於製造ic封裝件的方法和系統 - Google Patents
用於製造ic封裝件的方法和系統 Download PDFInfo
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- TWI431699B TWI431699B TW099129733A TW99129733A TWI431699B TW I431699 B TWI431699 B TW I431699B TW 099129733 A TW099129733 A TW 099129733A TW 99129733 A TW99129733 A TW 99129733A TW I431699 B TWI431699 B TW I431699B
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- Prior art keywords
- lead frame
- metal
- metal lead
- contact pads
- leadframe
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- 238000000034 method Methods 0.000 title claims description 55
- 238000004519 manufacturing process Methods 0.000 title description 28
- 239000002184 metal Substances 0.000 claims description 112
- 229910052751 metal Inorganic materials 0.000 claims description 112
- 238000005530 etching Methods 0.000 claims description 29
- 239000000463 material Substances 0.000 claims description 25
- 150000001875 compounds Chemical class 0.000 claims description 16
- 238000007747 plating Methods 0.000 claims description 16
- 238000000059 patterning Methods 0.000 claims description 5
- 230000008878 coupling Effects 0.000 claims description 2
- 238000010168 coupling process Methods 0.000 claims description 2
- 238000005859 coupling reaction Methods 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims 3
- 229910000679 solder Inorganic materials 0.000 description 33
- 239000011248 coating agent Substances 0.000 description 27
- 238000000576 coating method Methods 0.000 description 27
- 235000012431 wafers Nutrition 0.000 description 17
- 238000005538 encapsulation Methods 0.000 description 6
- 238000000465 moulding Methods 0.000 description 6
- 238000010019 resist printing Methods 0.000 description 6
- 239000000126 substance Substances 0.000 description 6
- 239000010949 copper Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 238000011161 development Methods 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 4
- 238000003848 UV Light-Curing Methods 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 239000011253 protective coating Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 229910001092 metal group alloy Inorganic materials 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000007921 spray Substances 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 238000011282 treatment Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 229930040373 Paraformaldehyde Natural products 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 238000007730 finishing process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000011900 installation process Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- -1 polyoxymethylene Polymers 0.000 description 1
- 229920006324 polyoxymethylene Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
- H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
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- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
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- H01L2224/321—Disposition
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- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/4809—Loop shape
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- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
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- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
本案係關於積體電路(IC)封裝技術,且尤其(但不限於)係關於用於圖案化IC封裝引線框架之系統及方法。
本專利申請案主張2009年9月2日申請之美國臨時專利申請案第61/239,421號的優先權,該臨時專利申請案據此以引用的方式併入本文中。
IC封裝為在IC器件製造中所涉及的最後階段之一。在IC封裝期間,一或多個IC晶片被安裝於封裝基板上,連接至電觸點,接著用包括電絕緣體之包封材料塗覆,該電絕緣體例如環氧樹脂或聚矽氧模製化合物。所得IC封裝件可接著安裝於印刷電路板(PCB)上及/或連接於其他電子組件。
時常地,無引線之IC封裝件可包括電觸點而非外部引線,其中該等電觸點在頂部上被包封材料覆蓋,而在IC封裝件之底部上裸露,以使得其能夠連接至位於IC封裝件下面之電子組件。時常地,使用金屬引線框架來形成IC封裝件之一部分可比使用層壓板或條帶材料(tape material)更有成本效益,此係因為例如可使用更有成本效益之材料,例如銅、鎳、或其他金屬或金屬合金,且使用此等材料可允許使用更有成本效益的製造方法,例如衝壓或蝕刻,而非多步層壓法。
在過去,無引線之IC封裝件受限之原因在於能夠用來將電信號傳遞至IC晶片之I/O埠及自IC晶片之I/O埠傳遞電信號的最多的端子數量限於可位於晶粒附著墊(Die-Attach Pad,DAP)周邊周圍之端子數量。已嘗試增加可用於與IC晶片之I/O埠電連接的端子數量,包括為了在DAP周邊周圍安裝較多端子而減小端子之間的距離及增加安置在DAP周邊周圍之端子列數。然而,增加端子列數要求減小IC晶片之尺寸抑或增加IC封裝件之尺寸。此外,端子之間能夠被縮短的距離量限於PCB上連接點之間的最小距離,此距離相對較大。
涵蓋本申請案中揭示之多種實施例。
以上對本發明之概述不意欲代表本發明之每一實施例或每一態樣。
當結合附圖考慮時,參考以下[實施方式],可對本發明之各種實施例有更完整的理解。
現將參考附圖更全面地描述本發明之各種實施例。然而,本發明可以各種不同形式實施,且不應理解為限於本文所述之實施例;更確切而言,提供該等實施例,以使得本揭示案將為全面且完整的,且可將本發明之範疇充分傳達給熟習此項技術者。
現參考圖1,圖上顯示例如可用於IC封裝件製造過程中之類型的金屬條100。金屬條100包括複數個器件區域101安置在其上面。在一些實施例中,金屬條100可為銅或其他金屬或金屬合金,且可具有5密耳、大於5密耳或小於5密耳之厚度。在各種實施例中,器件區域101之尺寸可變化,且金屬條100上之器件區域101的數目亦可變化。例如,在一些實施例中,金屬條100上之器件區域101的數量可為少於100個至多於1000個之任何數量。在IC製造過程期間,一或多個IC晶片可附接至各器件區域101且包封在包封化合物內。在各種實施例中,IC晶片可經由焊線(wire bond)電耦合至器件區域101或以倒裝晶片之構造直接耦合至彼處。IC製造過程還可包括使器件區域101彼此間單一化(singulate),以形成複數個IC封裝件,其可經配置而安裝至例如PCB之外部器件。當IC封裝件被安裝至PCB上時,IC晶片可經由安置在IC封裝件底部表面上之接觸區域電耦合至PCB。
現參考圖2A-2E,圖上顯示在製造過程之各個階段時IC封裝件之一實施例的各態樣。出於說明之目的,關於單個IC封裝件描述製造過程,但是在各種實施例中,製造過程之各步驟可應用至引線框架條(例如圖1所示之金屬條100)之複數個器件區域中的一些或全部區域。現參考圖2A,製造過程開始於未蝕刻之引線框架200,例如金屬條之器件區域。在圖2B中,引線框架200已被部分蝕刻而在其頂部表面上形成界定金屬跡線222之凹進處226的圖案。在所示實施例中,金屬鍍層已被添加至安置在金屬跡線222頂部表面上之接合區域218。接合區域218之金屬鍍層可藉由將可接合或可焊接的材料施加至金屬跡線222來形成,該材料例如有電鍍金屬或包層金屬,例如銀(Ag)、金(Au)、錫(Sn)、銅(Cu)或其他可接合的材料。在一些實施例中,金屬跡線222之底部表面的若干部分可被塗有可焊接的材料,例如金屬鍍層。正如下文中更詳細之描述般,在此實施例中稍後將成為接觸墊206的底部表面之區域被電鍍。在圖2C中,IC晶片204已使用黏合材料(例如環氧樹脂)而被固定至引線框架200之頂部表面,例如經由焊線214電耦合至接合區域218,且已應用包封化合物208(顯示為陰影區域)來包封IC晶片204及焊線214。此外,包封化合物208亦填充於凹進處226中,包括安置在IC晶片204下面之凹進處226。
在圖2D中,引線框架200之底部表面已被蝕刻掉。在所示實施例中,引線框架200已在其整個底部表面上被蝕刻而移除其部分200a。在各種實施例中,可蝕刻掉整個底部表面之子集。如與圖2C相比在圖2D中可見,,引線框架之厚度已減小。正如下文中更詳細之描述般,藉由自整個底部表面上減小引線框架200之厚度,若存在隨後之部分或圖案化蝕刻,則在隨後之部分或圖案化蝕刻期間,將需要蝕刻掉較少材料,此可減少底切,從而改善電連通性,且在一些實施例中,可允許形成較薄之接觸墊。例如,在一些實施例中,引線框架200可具有大約4密耳之厚度,且該厚度可被減小大約1密耳或更多。
現參考圖2E,引線框架200之底部表面已被部分蝕刻而在其中形成一圖案。在各種實施例中,安置在引線框架200底部表面上之接觸墊206可被鍍上金屬鍍層。在各種實施例中,底部表面之蝕刻可包括蝕刻對應於在引線框架200頂部表面中形成之凹進處226的引線框架200之部分226a,以在彼等區域處完全蝕刻穿過引線框架200,且在一些位置處,曝露包封化合物208之底部表面。在各種實施例中,蝕刻除了引線框架200在凹進處226下面介於金屬跡線222之間的部分226a區域之外還可包括移除一些金屬跡線222之區域222a。在一些實施例中,保護塗層229可添加至金屬跡線222之一部分底部表面上。
現參考圖3A,圖上顯示在安裝上IC晶片之前的引線框架300之俯視圖。在所示實施例中,引線框架300具有在其頂部表面中蝕刻出之複數個凹進處326(顯示為無陰影部分),其中凹進處326在引線框架300之頂部表面上形成複數個金屬跡線322(顯示為陰影部分)。金屬跡線322可形成為具有任何尺寸之任何寬度,例如在一些實施例中,金屬跡線322之寬度可大約為1.5密耳,且其彼此間可相隔大約4密耳。雖然顯示具有特定圖案之實施例,但是可在引線框架300中蝕刻出任何數量的圖案。用於焊線接合至IC晶片之接合區域318可包括金屬跡線322在引線框架300周邊周圍之部分,且可包括其上的金屬鍍層(未顯示)。出於說明之目的,接觸墊306的安置在引線框架300底部表面上以用於將IC晶片電耦合至PCB上之相應觸點的位置被顯示為安置在金屬跡線322的與接合區域318相對之一端上的無陰影正方形。引線框架300介於凹進處326之間的一些未蝕刻部分可用來為可安裝在其上面之IC晶片提供支撐及/或提供電子路徑以在引線框架300頂部表面上之接合區域318與引線框架300底部表面上之接觸墊306之間發送信號。雖然圖上顯示所有接觸墊306相對於接合區域318安置在內部,但是一些或所有接觸墊306可直接安置在接合區域318下面,或可自接合區域318向外朝引線框架300之周邊安置。
圖3B為引線框架300的來自圖3A細節A之部分的放大橫截面側視圖。自此視圖可觀察到在引線框架300之頂部表面中形成的凹進處326以及安置在其之間的金屬跡線322及接合區域318。雖然圖上顯示凹進處326具有確定的深度及寬度,但是在各種實施例中,凹進處326可視設計標準而定,具有任何深度及任何寬度。在各種實施例中,當藉由在引線框架300之頂部表面上部分地蝕刻圖案而形成接合區域318及金屬跡線322時,可能在金屬跡線322之側面的部分322a被移除的位置處發生底切,因此使金屬跡線322在上表面下面之部分比上表面窄。
現參考圖4A,圖上顯示引線框架400具有在其頂部表面中蝕刻出之圖案的一實施例之俯視圖。出於說明之目的,顯示安裝在該框架上之IC晶片404的輪廓。在此實施例中,藉由蝕刻掉引線框架400之頂部表面的若干部分來形成凹進處426,以界定接合區域416及418以及金屬跡線422。在所示實施例中,晶粒附著區(DA區)為引線框架的在將要安裝IC晶片404之區域下面的部分,且可包括晶粒附著墊與金屬跡線422之若干部分兩者。
仍然參考圖4A,出於說明之目的,可在蝕刻步驟期間於引線框架400之底部表面上安置接觸區域的區域之輪廓被顯示為具有虛線之圓圈。如圖可見,引線框架400之頂部表面已被部分地蝕刻,以便形成兩列接合區域416及418。在所示實施例中,內部之一列接合區域418的尺寸及形狀不同於外部之一列接合區域416的尺寸及形狀。在所示實施例中,無金屬跡線耦合至外部之一列接合區域416,因為如圖可見,接合區域416被直接安置在接觸墊上。在此定向時,接合區域416之中心線間必須相隔與接觸墊中心線之間的距離相同之距離。然而,在內部之一列中,接合區域418彼此間相隔得更緊密,因為一些接觸墊不直接安置在相應的接合區域418之下面。
現參考圖4B,圖上顯示圖4A之引線框架400的替代性實施例。在此實施例中,已形成之外部的一列接合區域416實質上小於顯示為直接安置在其下面之接觸墊406。
現參考圖5,圖上顯示在製造過程之各個階段時對應於圖4A之細節A及細節B的橫截面側視圖。在步驟s501時,將耐蝕刻的材料選擇性地施加至金屬引線框架500之頂部表面,且在引線框架500之頂部表面中部分地蝕刻出凹進處526以在其中形成圖案。在一些實施例中,耐蝕刻的塗層可如圖所示相對於接合區域516,選擇性地施加至引線框架500之頂部表面與底部表面兩者上。在一些實施例中,耐蝕刻的塗層可為金屬鍍層,或可在已形成凹進處526之後施加金屬鍍層。在步驟s503時,用包封化合物508覆蓋引線框架500之頂部表面。在各種實施例中,在施加包封化合物508之前,焊線(未顯示)可接合至接合區域516及518。在步驟s505時,部分地蝕刻引線框架500之底部表面而移除其某些部分,以在其中界定具有側壁506a之接觸墊506。如圖可見,蝕刻引線框架500之底部表面來界定接觸區域506使得其側壁506a的若干部分被蝕刻掉或底切。
仍然參考圖5,對應於細節A之側視圖顯示接觸墊506被直接安置在接合區域516下面,兩者具有實質上相同的直徑。時常地,PCB安裝要求規定接觸區域506之最小直徑及其必須被隔開的距離(間距)。因而,將接觸區域506直接安置在相應接合區域516下面要求接合區域516滿足彼等相同之PCB限制性。相比之下,對應於細節B之側視圖顯示兩個外部接觸墊506安置在接合區域518a下面,而對應於接合區域518b之接觸墊(未顯示)自彼處遠距離地安置且經由金屬跡線522耦合至彼處。藉由遠距離地安置對應於接合區域518b之接觸墊,接合區域518a及518b可具有比細節A中所示之接合區域516小的寬度且彼此間相隔得更緊密,但仍然滿足關於相應接觸墊506之PCB間隔要求。例如,在一些實施例中,接合區域518a及518b可具有大約2.5密耳之寬度且可相隔大約4密耳,而接觸墊506可具有大約6密耳之直徑且相隔大約4密耳或更多。
現參考圖6A及6B,圖上顯示在兩種不同IC封裝件製造過程之各個階段時IC封裝件之側視圖。現參考圖6A,在步驟s601時,引線框架600之側視圖顯示在其頂部表面中具有複數個凹進處,從而在其上面界定複數個接合區域,且具有添加至彼處之包封層。在步驟s603時,將塗層660選擇性地施加至引線框架600之底部表面,該塗層例如有金屬鍍層、耐蝕刻塗層或其他材料。在步驟s605時,部分蝕刻引線框架600之底部表面而在其中形成對應於上面不具有選擇性塗層660之部分的凹進處。在所示實施例中,該等凹進處界定具有側壁606a之複數個接觸墊,其中部分蝕刻在側壁606a中引起蝕刻底切。在各種實施例中,引線框架600越厚,底切將在接觸墊之側壁606a中延伸得越深。
現參考圖6B,在步驟s601'時,引線框架600之側視圖顯示在其頂部表面中具有複數個凹進處,從而在其上面界定複數個接合區域,且具有添加至彼處之包封層。在所示實施例中,已移除引線框架600之底部部分600a,從而將引線框架600之厚度自第一量減小至第二量。在各種實施例中,底部部分600a可經由機械或化學蝕刻或研磨法來移除。在步驟s603'時,將塗層660選擇性地施加至引線框架600之底部表面,該塗層例如有金屬鍍層、耐蝕刻塗層或其他材料。在步驟s605'時,部分蝕刻引線框架600之底部表面而移除引線框架600的未被選擇性塗層660覆蓋之部分,從而在引線框架600中形成凹進處。在所示實施例中,凹進處界定具有側壁606a'之複數個接觸墊,其中部分蝕刻在側壁606a'中引起蝕刻底切。如圖可見,因為自引線框架600之底部表面移除部分600a,所以側壁606a'之底切的量相對於圖6A所示之底切已有減少。
現參考圖7A,圖上顯示在製造過程之各個階段時金屬引線框架700的橫截面側視圖。在步驟s703時,將金屬塗層760選擇性地施加至金屬引線框架700之底部表面。在步驟s705時,部分蝕刻金屬引線框架700之底部表面而界定接觸墊706,各接觸墊706具有在其底部表面中形成之圖案。在所示實施例中,接觸墊706各具有在其內部形成的凹槽763,凹槽763一般為拋物線狀的凹形。
現參考圖7B,更詳細地描述圖7A之接觸墊706之一。在步驟s707時,接觸墊706之透視圖及側視圖顯示具有相對於彼處安置之焊接劑765(出於說明之目的,顯示為焊球)。在各種實施例中,可使用焊料絲網印刷方法、浸焊、焊膏、焊球或其他焊接精加工法來施加焊接劑765。如圖可見,接觸墊706之底部表面中的凹槽763可適合於為與焊接劑765之接合提供增加的表面面積。在各種實施例中,焊接劑765可為焊球、焊線、焊膏或其他附著材料。在步驟s709時,將焊接劑765接合至接觸墊706之凹槽763的表面。在一些實施例中,焊接劑765可在安裝至PCB之前或在安裝過程期間施加至接觸墊706。
現參考圖8A,圖上顯示在製造過程之各個階段時金屬引線框架800的橫截面側視圖。在步驟s803時,將金屬塗層860選擇性地施加至金屬引線框架800之底部表面。在步驟s805時,選擇性地蝕刻金屬引線框架800之底部表面而界定接觸墊806,各接觸墊806具有在其底部表面中形成之圖案。在所示實施例中,接觸墊806各具有在其內部形成的複數個凹槽863。
現參考圖8B,更詳細地描述圖8A之接觸墊806之一。在步驟s807時,接觸墊806之透視圖顯示具有相對於彼處安置之焊接劑865。如在此實施例中可見,接觸墊806之底部包括圍繞凹坑形凹槽863a之環形通道凹槽863b。在步驟s809時,使焊接劑865熔化以符合接觸墊806之凹槽863。在各種實施例中,具有複數個凹槽863使接觸墊806與焊接劑865之間的接觸表面面積增加。
現參考圖9,圖上顯示IC封裝件製造過程900之一實施例的流程圖。該過程以步驟902開始於未蝕刻之引線框架,例如銅製金屬條。在步驟904時,在頂部表面上部分蝕刻引線框架,以在其中形成凹進處,從而在其上面界定金屬跡線。該部分蝕刻可藉由許多蝕刻方法來實現,例如用一層光可成像耐蝕刻劑(例如光可成像環氧樹脂)塗覆或層壓引線框架之頂部表面。例如,可將光阻材料旋轉塗覆至引線框架上,然後使用光工具曝露於紫外光,其中接著在顯影過程中移除所曝露之部分。由此圖案化耐蝕刻劑,以在引線框架之頂部表面上提供凹進處。接著例如藉由浸漬或加壓噴霧來蝕刻引線框架,以部分圖案化金屬跡線。在一些實施例中,蝕刻可為半蝕刻,以便使在引線框架中形成之凹進處延伸穿過其一半長度。例如,在4密耳之引線框架中,半蝕刻將為2密耳的蝕刻。在各種實施例中,引線框架可被蝕刻得超過或少於其一半長度。例如,在一些實施例中,部分蝕刻可達至大約為3密耳+/- 0.5密耳之深度。在蝕刻後,可剝掉耐蝕刻材料。
在步驟906時,可選擇性地電鍍經部分蝕刻之引線框架,例如藉由電鍍其頂部表面上之接合區域來進行。接合區域之金屬鍍層可藉由將可接合材料施加至金屬跡線而形成。在各種實施例中,用以增加黏附力之表面黏附增強處理(「AE處理」)(例如粗糙化及/或清潔表面)可在金屬電鍍之後進行。
在步驟908時,將IC晶片使用黏合材料(例如環氧樹脂)安裝至引線框架。在將IC晶片安裝至引線框架後,IC晶片可例如經由焊線結合電耦合至安置在晶粒附著區外部之接合區域。在各種實施例中,可利用倒裝晶片之構造,且可不需要焊線接合。此後,在步驟910時,應用模製化合物來包封IC晶片及焊線。在步驟912時,蝕刻引線框架之底部表面。在一些實施例中,在步驟912時不進行蝕刻。在一些實施例中,在整個底部表面上蝕刻引線框架,從而減小引線框架之厚度。藉由在引線框架之整個底部表面上減小引線框架之厚度,若存在隨後之部分或圖案化蝕刻,則在隨後之部分或圖案化蝕刻期間,需要蝕刻掉較少材料,從而減少底切現象。在各種實施例中,在步驟912時,只有子集而非整個底部表面可被背面蝕刻,例如以預定圖案來進行。
在各種實施例中,過程900可在步驟912之後結束。在一些實施例中,過程900進行至步驟914。在一些實施例中,在過程900進行至步驟914之前,將完全的金屬電鍍施加至引線框架之底部表面。在步驟914時,用材料選擇性地塗覆引線框架之底部表面。在一些實施例中,塗覆材料可為印刷在引線框架之底部表面上的阻焊劑。在曝露阻焊劑及顯影後,過程900可結束。在一些實施例中,塗覆材料可為施加至引線框架之底部表面的耐蝕刻劑,例如藍墨印刷,其用以轉移欲用例如FeCl3
之蝕刻劑蝕刻的圖案之影像。在一些實施例中,塗覆材料為在步驟912後施加至引線框架之底部表面的金屬鍍層,例如NiPdAu鍍層。在一些實施例中,過程900在金屬電鍍後結束,可進行至以上描述之阻焊劑印刷步驟,或可進行至以上描述之耐蝕刻劑步驟。
在一些實施例中,在已用材料塗覆引線框架之底部表面後,過程900進行至步驟916。在步驟916時,部分蝕刻引線框架之底部表面而在其中形成圖案。在金屬鍍層選擇性地施加至引線框架之底部表面的實施例中,可能不需要耐蝕刻劑,可能不需要施加在金屬鍍層上,或可能施加至金屬鍍層上。在部分蝕刻之後,若有藍墨突出物,則執行「噴砂(de bleed)」步驟來移除藍墨突出物。在一些實施例中,若應用藍墨,則藍墨可能會留在金屬鍍層上或可添加至金屬鍍層以保護金屬鍍層免受後續處理步驟的影響。在各種實施例中,底部表面之背面蝕刻可包括蝕刻引線框架的對應於在引線框架頂部表面中形成之凹進處的部分,進而在彼等區域處完全地蝕刻穿過引線框架,且進而裸露包封化合物之底部表面。在各種實施例中,背面蝕刻除了引線框架介於金屬跡線之間的區域之外還可包括移除一些金屬跡線之區域。在各種實施例中,根據確定的設計標準之需要,可重複多次該背面蝕刻。
在一些實施例中,保護塗層可添加至引線框架之一部分底部表面。例如,在一些實施例中,在步驟918時,阻焊劑可印刷至金屬跡線之底部表面的若干部分,以覆蓋其裸露部分。此後,在步驟920時,過程900可包括化學去毛邊(chemical de flash),以移除接觸區域上之任何抗焊劑,同時在裸露金屬跡線上留下抗焊劑。接著可固化抗焊劑,例如經由UV固化來實現,因而,抗焊劑可耐受焊料及化學製品。在步驟922時,若有剩餘藍墨,則可接著剝離剩餘藍墨而曝露接觸表面之區域以在有需要時用於進一步的表面安裝處理。
現參考圖10,圖上顯示圖9之IC封裝件製造過程900的一替代性實施例之流程圖。類似於圖9之過程,所示實施例之IC製造過程1000以步驟1002開始於未蝕刻之引線框架,隨後為在步驟1004時之部分蝕刻。在步驟1006時,經部分蝕刻之引線框架可在其頂部表面與底部表面兩者上被選擇性地電鍍。接著,在步驟1008時,將IC晶片安裝至引線框架且電耦合至彼處。此後,在步驟1010時,施加模製化合物來包封IC晶片及焊線。在步驟1012時,部分蝕刻引線框架之底部表面。在各種實施例中,在步驟1014時,噴水或其他研磨過程可施加至引線框架之底部表面。
在各種實施例中,過程1000可在步驟1014之後結束。在一些實施例中,過程1000進行至步驟1016且在其上面印刷阻焊劑,然而在其他實施例中,過程1000可進行至步驟1016'且可施加耐蝕刻材料。自步驟1016開始,過程1000之各種實施例可包括類似於以上圖9中描述之步驟的化學去毛邊(步驟1018)、UV固化(步驟1020)及/或藍墨剝離(步驟1022)。自步驟1016'開始,過程1000之各種實施例可包括類似於以上圖9中描述之步驟的阻焊劑印刷(步驟1018')、曝露(步驟1020')及/或顯影(步驟1022')。
雖然已在附圖中展示及在前述[實施方式]中描述了本發明之方法及系統的各種實施例,但是應瞭解,在不偏離本文所述之本發明精神的情況下,本發明不限於所揭示之實施例,而是能夠有許多重新排列、修改及替換。
100...金屬條
101...器件區域
200...引線框架
200a...部分
204...IC晶片
206...接觸墊
208...包封化合物
214...焊線
218...接合區域
222...金屬跡線
226...凹進處
222a...區域
226a...部分
229...保護塗層
300...引線框架
306...接觸墊
318...接合區域
322...金屬跡線
322a...部分
326...凹進處
400...引線框架
404...IC晶片
406...接觸墊
416...接合區域
418...接合區域
422...金屬跡線
426...凹進處
500...引線框架
506...接觸墊/接觸區域
506a...側壁
508...包封化合物
516...接合區域
518a...接合區域
518b...接合區域
522...金屬跡線
526...凹進處
600...引線框架
600a...底部部分
606a'...側壁
660...塗層/選擇性塗層
700...金屬引線框架
706...接觸墊
760...金屬塗層
763...凹槽
765...焊接劑
800...金屬引線框架
806...接觸墊
860...金屬塗層
863...凹槽
863a...凹坑形凹槽
863b...環形通道凹槽
865...焊接劑
900...IC封裝件製造過程
902...金屬引線框架
904...部分蝕刻
906...選擇性電鍍
908...晶粒附著及焊線接合
910...模製
912...蝕刻底部表面
914...選擇性塗覆底部表面
916...部分蝕刻底部表面
918...阻焊劑印刷
920...化學去毛邊
922...藍墨剝離
s501...步驟
s503...步驟
s505...步驟
s601...步驟
s603...步驟
s605...步驟
s601'...步驟
s603'...步驟
s605'...步驟
s703...步驟
s705...步驟
s707...步驟
s709...步驟
s803...步驟
s807...步驟
s809...步驟
1000...IC製造過程
1002...金屬引線框架
1004...部分蝕刻
1006...選擇性電鍍
1008...晶粒附著及焊線接合
1010...模製
1012...部分蝕刻底部表面
1014...噴水
1016...阻焊劑印刷
1016'...施加耐蝕刻劑
1018...化學去毛邊
1018'...阻焊劑印刷
1020...UV固化
1020'...曝露
1022...藍墨剥離
1022'...顯影
圖1展示用於IC封裝件製造過程中之引線框架條的一實施例;
圖2A-E展示在製造過程之各個階段時無引線之IC封裝件的一實施例之各態樣;
圖3A-B為在頂部表面上形成有複數個金屬跡線之金屬引線框架的一實施例之兩個視圖;
圖4A-B為在周邊周圍具有兩列接合區域(bonding area)之兩個引線框架的實施例之俯視圖;
圖5展示在製造過程之各個階段時圖4A之引線框架的實施例之細節A及細節B;
圖6A及6B展示在兩種製造過程之各個階段時IC封裝件之一實施例的各種態樣之側視圖;
圖7A-B展示在圖案化接觸墊之製造過程的各個階段時IC封裝件之一實施例的各種態樣之側視圖;
圖8A-B展示在圖案化接觸墊之製造過程的各個階段時IC封裝件之一實施例的各種態樣之側視圖;
圖9為製造IC封裝件之方法的一實施例之流程圖;及
圖10為製造IC封裝件之方法的各種實施例之流程圖。
900...IC封裝件製造過程
902...金屬引線框架
904...部分蝕刻
906...選擇性電鍍
908...晶粒附著及焊線接合
910...模製
912...蝕刻底部表面
914...選擇性塗覆底部表面
916...部分蝕刻底部表面
918...阻焊劑印刷
920...化學去毛邊
922...藍墨剝離
Claims (21)
- 一種形成IC封裝件之方法,該方法包括:提供金屬引線框架,其具有第一值之厚度;圖案化該金屬引線框架之頂部表面,以在其中形成凹進處,該等頂部表面之凹進處界定複數個接合區域;選擇性地電鍍該頂部表面;將IC晶片安裝至該頂部表面上;將該IC晶片電耦合至該複數個接合區域;包封該IC晶片於包封化合物中;藉由自該金屬引線框架之底部表面移除一層金屬來將該金屬引線框架之該厚度減小至第二值;選擇性地電鍍該金屬引線框架之該底部表面,以在其上面形成圖案,該圖案界定該金屬引線框架之欲被蝕刻的部分;選擇性地蝕刻該金屬引線框架之該等部分,以在其底部表面形成凹進處,該等底部表面之凹進處界定複數個相對於該引線框架之內部具有蝕刻底切的底部表面具有側壁之接觸墊;及其中藉由將該金屬引線框架之該厚度減小至該第二量來減小該底切之深度。
- 如請求項1之方法,其中該選擇性蝕刻在該複數個接觸墊之底部表面形成複數個凹槽。
- 如請求項2之方法,其中該選擇性蝕刻形成環繞該複數個凹槽中之至少一個凹槽的至少一個環形通道。
- 如請求項2之方法,其進一步包括:將可焊接之導電性材料施加至該複數個凹槽。
- 如請求項1之方法,其中該金屬引線框架之厚度的該第一值小於大約5密耳。
- 如請求項1之方法,其中該第一值與該第二值之間的差值大於大約1密耳。
- 一種圖案化積體電路(IC)封裝件之底部表面的方法,該積體電路封裝件為如下類型:所具有之IC晶片被安裝至金屬引線框架且電耦合至安置在該金屬引線框架頂部表面上之接合區域,該IC晶片被包封於包封化合物中,該方法包括:自該金屬引線框架之實質上整個底部表面移除一層金屬,以曝露該金屬引線框架之一表面;將耐蝕刻材料施加至該金屬引線框架之該被曝露的表面,以在其上面形成圖案,該圖案界定該金屬引線框架之欲被蝕刻的部分;選擇性地蝕刻該金屬引線框架之由該圖案界定的該等部分,以電氣隔離複數個接觸墊且在該複數個接觸墊之底部表面中形成凹槽,該複數個接觸墊具有內部具有蝕刻底切之側壁;及其中藉由自該金屬引線框架之實質上整個底部表面移除該層金屬來減小該等側壁中的該蝕刻底切之深度。
- 一種積體電路(IC)封裝件,包括:金屬引線框架,其在其頂部表面及底部表面上具有凹進處之圖案,該金屬引線框架之該頂部表面上之該等凹進處界定複數個接合區域,且該金屬引線框架之該底部表面上之該等凹進處界定電耦合至該等接合區域之複數個接觸墊,各接觸墊具有在其底部表面中蝕刻出之凹槽;IC晶片,其被安裝至該金屬引線框架且電耦合至該等接合區域,該IC晶片被包封於包封化合物中;及可焊接之導電性材料,其填充各接觸墊之該凹槽。
- 如請求項8之IC封裝件,其中該複數個接觸墊中之至少一個接觸墊具有在其底部表面中蝕刻出且環繞該凹槽之環形通道。
- 如請求項8之IC封裝件,其中至少一個接合區域之表面面積小於電耦合至彼處之接觸墊的表面面積。
- 如請求項8之IC封裝件,其中在該等接觸墊中之至少一個接觸墊中蝕刻出的該凹槽一般為拋物線狀的凹形。
- 一種圖案化積體電路(IC)封裝件之底部表面的方法,該積體電路封裝件為如下類型:所具有之IC晶片被安裝至金屬引線框架且電耦合至安置在該金屬引線框架頂部表面上之接合區域,該IC晶片被包封於包封化合物中,該方法包括:將耐蝕刻層施加至該IC封裝件之該金屬引線框架的底部表面,以在其上面形成圖案,該圖案界定該金屬引線框架之欲被蝕刻的部分;選擇性地蝕刻該金屬引線框架之由該圖案界定的該等部分,以電氣隔離複數個接觸墊且在該複數個接觸墊之底部表面中形成凹槽;及將可焊接之導電性材料施加至該複數個接觸墊之底部表面。
- 如請求項12之方法,其進一步包括:在施加該耐蝕刻層至彼處之前,在該金屬引線框架之實質上整個底部表面上移除該金屬引線框架之一個層。
- 如請求項12之方法,其中施加該耐蝕刻層包括施加金屬鍍層。
- 如請求項12之方法,其中施加該耐蝕刻層包括將該耐蝕刻層施加至該金屬引線框架之該頂部表面與該底部表面兩者上。
- 如請求項12之方法,其中施加該耐蝕刻劑包括形成具有外部周邊及內部周邊之至少一個耐蝕刻劑環。
- 如請求項16之方法,其中該選擇性蝕刻形成由該環之該外部周邊界定的該複數個接觸墊之一個接觸墊之外邊緣,且形成由該環之該內部周邊界定的凹槽。
- 如請求項16之方法,其中該外部周邊及該內部周邊為圓周。
- 如請求項12之方法,其中施加該耐蝕刻劑包括形成耐蝕刻劑內環及與該至少一個內環同心之耐蝕刻劑外環。
- 如請求項19之方法,其中該選擇性蝕刻形成由該外環之外部周邊界定的該複數個接觸墊之一個接觸墊之外邊緣、由該內環之內部周邊界定的凹槽,及由介於該內環與該外環之間的區域界定之環形通道。
- 如請求項12之方法,其進一步包括:自一長條的IC封裝件中單一化該IC封裝件。
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US23942109P | 2009-09-02 | 2009-09-02 | |
PCT/CN2009/001320 WO2011026261A1 (en) | 2009-09-02 | 2009-11-26 | Ic package and method for manufacturing the same |
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- 2009-11-26 KR KR1020127008136A patent/KR101668141B1/ko active IP Right Grant
- 2009-11-26 CN CN200980161204.0A patent/CN102576701B/zh not_active Expired - Fee Related
- 2009-11-26 US US13/389,935 patent/US9362138B2/en active Active
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TW201126618A (en) | 2011-08-01 |
CN102576701B (zh) | 2016-08-17 |
KR101668141B1 (ko) | 2016-10-20 |
CN102576701A (zh) | 2012-07-11 |
US9362138B2 (en) | 2016-06-07 |
KR20120085761A (ko) | 2012-08-01 |
WO2011026261A1 (en) | 2011-03-10 |
US20120181680A1 (en) | 2012-07-19 |
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