WO2006040419A1 - Procede d'obtention de couches localisees sur un circuit hybride - Google Patents
Procede d'obtention de couches localisees sur un circuit hybride Download PDFInfo
- Publication number
- WO2006040419A1 WO2006040419A1 PCT/FR2004/002603 FR2004002603W WO2006040419A1 WO 2006040419 A1 WO2006040419 A1 WO 2006040419A1 FR 2004002603 W FR2004002603 W FR 2004002603W WO 2006040419 A1 WO2006040419 A1 WO 2006040419A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- face
- circuit
- substrate
- hybrid circuit
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to a method for obtaining localized layers on a hybrid circuit.
- the invention is part of the microelectronics techniques for accurately locating, on a substrate (generally a semiconductor plate), at least one pattern of a material forming a layer, for example a thin layer.
- the invention applies in particular to semiconductor plates forming, for example, reading circuits on which chips (chips) are hybridized, for example optoelectronic chips, on each of which it is desired to locate at least one layer of a given material, for example an anti-reflection layer.
- Figure 1 schematically illustrates the problem of obtaining localized layers on a hybrid circuit.
- FIG. 1 shows a substrate 2 on which its hybridized chips 4 for example by a technique called flip-chip.
- This hybridization can be obtained by means of microballs of solder (solder microballs ”) or by the ACF technique (for Anisotropy Conductive Films) or by gluing. It is desired to cover the rear face of each chip 4 with a layer 6 which may be a thin layer and which is made of a determined material, as shown schematically in FIG.
- each thin layer 6 stops, with great precision, at the edges of the corresponding chip 4.
- the first known technique is to deposit each thin layer 6 on the rear face of the corresponding chip 4 before cutting this chip and therefore before hybridization thereof.
- FIG. 1 The second known technique, which is the most precise of the three, is schematically illustrated by FIG.
- the substrate 1, on which each chip 4 is hybridized is covered with a layer 8 of photosensitive resin ("photoresist").
- the excess material is then removed from the non-irradiated areas by the so-called lift-off technique.
- the third known technique is schematically illustrated in FIG. 4.
- This cache is provided with a window facing each chip 4.
- This cover is fixed to the substrate 2 by means not shown, by aligning the cache 16 and the substrate 2 with great accuracy.
- a thin layer 18 of the material is then deposited on the rear face of each chip 4 through this cover 16.
- the technique of deposition before hybridization thus consists in depositing the thin layer on the back-side of the chips before hybridization thereof.
- the second and third known techniques are masking techniques.
- the mask masking technique is imprecise and one can not guarantee an accuracy better than 20 ⁇ m on the realization of a cache and its alignment with respect to the substrate.
- the present invention aims to overcome the above disadvantages.
- this hybrid circuit comprising a substrate and at least one elementary circuit, this elementary circuit comprising a first face and a second face via it is hybridized to one side of the substrate, this method being characterized in that it comprises the following steps:
- a first layer is formed on the hybrid circuit so that this first layer covers this face of the substrate and each elementary circuit, the first layer of the first face of each elementary circuit is eliminated, a part of this first layer remaining on the hybrid circuit,
- a second layer is formed on the hybrid circuit so that this second layer covers this first face and this part of the first layer
- this second layer is a thin layer, that is to say a layer whose thickness is less than 2 microns.
- the first layer is removed, by polishing, from the first face of each elementary circuit.
- Said part of the first layer can be removed chemically or by means of a plasma.
- the first layer may be a polymer layer.
- the second layer may be an anti-reflective layer or a metal layer.
- the invention has various advantages which are indicated below.
- the invention is useful in cases where the first technique is not, especially when the hybridized chips must be thinned to very small thicknesses that require thinning after hybridization.
- the invention also has advantages related to accuracy. Indeed, unlike the second and third known techniques, the invention allows a perfect alignment of a thin layer and the top of an elementary circuit such as a chip 2 of Figure 2.
- the invention also has advantages as regards simplicity and apparatus for its implementation.
- the first layer which is for example a polymer layer, can be spread extremely imprecisely and have a large thickness since this first layer has only a protective function (and is not used for photolithography ).
- the method which is the subject of the invention is furthermore usable in all plate / plate equipment (allowing spreading, polishing and deposition).
- the invention also has advantages over known techniques with regard to the cost of implementation.
- FIG. 1 already described, schematically represents a substrate and chips hybridized to this substrate
- FIG. 2 already described, schematically shows layers located on these chips
- FIGS. 3 and 4 already described, schematically illustrate known techniques for obtaining the hybrid circuit shown in FIG. 2; and FIGS. 5 to 8 schematically illustrate steps of an implementation mode. particular of the method which is the subject of the invention.
- FIGS. 5 to 8 there is available a hybrid circuit comprising, as seen in FIG. 5, a substrate 20 and an elementary circuit or a plurality of elementary circuits 22.
- Each elementary circuit 22 is hybridized, by its lower face, to a face of the substrate 20 and it is desired to form a layer made of a determined material and located on the upper face of each elementary circuit.
- the substrate 20 is a silicon plate 100 mm in diameter and each elementary circuit 22 is an optoelectronic circuit.
- a layer 24 made of a polymer is deposited on the upper face of the substrate, on which the circuit 22 is hybridized.
- This polymer layer 24 thus covers this upper face of the substrate and these circuits 22.
- the polymer is a photosensitive resin which is spread by spinning to give it a thickness of 5 microns.
- the photoresist layer is then dried.
- a second step schematically illustrated in FIG. 6, the upper face of the substrate 20, provided with the circuits 22 and the polymer layer 24, is subjected to mechanical polishing, for example by means of a standard polishing machine. to eliminate all the polymer layer which covers the upper face of each circuit 22 and a thickness of this circuit 22.
- the polishing takes place over a thickness of 50 ⁇ m when the thickness of the polymer layer is 5 ⁇ m.
- the entire substrate 20 is covered with a thin layer 28 whose thickness is for example 0.5 ⁇ m and which is for example an anti-reflection layer.
- a thin film deposition machine is used which is loaded cassette by cassette. 004/002603
- the remaining portions of the polymer layer 24 are decomposed, for example chemically or by means of a plasma (or in any other way) and, when they are decomposed, involve the parts of the thin layer 28 which are located above these remaining portions of the polymer layer.
- the so-called "lift-off” technique is used to eliminate the photosensitive resin (for example by means of acetone).
- This hybridization is done by the technique of flip-chip and by means of microbeads.
- a transmitter circuit for example VCSEL
- a detector circuit in the infrared range or the visible range for example
- An important application of the invention is the deposition, in the case of an infrared coated-thin component, of a layer of anti-reflection material on the rear face of the detection zone of this component.
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007536207A JP4638501B2 (ja) | 2004-10-13 | 2004-10-13 | ハイブリッド回路上に画定される層の製造方法 |
US11/576,056 US7759261B2 (en) | 2004-10-13 | 2004-10-13 | Method for producing layers located on a hybrid circuit |
PCT/FR2004/002603 WO2006040419A1 (fr) | 2004-10-13 | 2004-10-13 | Procede d'obtention de couches localisees sur un circuit hybride |
EP04791517A EP1800338A1 (fr) | 2004-10-13 | 2004-10-13 | Procede d'obtention de couches localisees sur un circuit hybride |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/FR2004/002603 WO2006040419A1 (fr) | 2004-10-13 | 2004-10-13 | Procede d'obtention de couches localisees sur un circuit hybride |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2006040419A1 true WO2006040419A1 (fr) | 2006-04-20 |
Family
ID=34959528
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/FR2004/002603 WO2006040419A1 (fr) | 2004-10-13 | 2004-10-13 | Procede d'obtention de couches localisees sur un circuit hybride |
Country Status (4)
Country | Link |
---|---|
US (1) | US7759261B2 (fr) |
EP (1) | EP1800338A1 (fr) |
JP (1) | JP4638501B2 (fr) |
WO (1) | WO2006040419A1 (fr) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4963389A (en) * | 1985-02-22 | 1990-10-16 | Mitsubishi Denki Kabushiki Kaisha | Method for producing hybrid integrated circuit substrate |
JPH05175629A (ja) * | 1991-12-24 | 1993-07-13 | Mitsubishi Electric Corp | 混成集積回路装置 |
US5661343A (en) * | 1994-03-16 | 1997-08-26 | Hitachi, Ltd. | Power hybrid integrated circuit apparatus |
US6467674B1 (en) * | 1999-12-09 | 2002-10-22 | Casio Computer Co., Ltd. | Method of manufacturing semiconductor device having sealing film on its surface |
FR2858716A1 (fr) * | 1997-11-20 | 2005-02-11 | Commissariat Energie Atomique | Procede d'obtention de couches localisees sur un circuit hybride |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01218042A (ja) | 1988-02-26 | 1989-08-31 | Nec Corp | 半導体装置 |
US5308742A (en) | 1992-06-03 | 1994-05-03 | At&T Bell Laboratories | Method of etching anti-reflection coating |
FR2715002B1 (fr) | 1994-01-07 | 1996-02-16 | Commissariat Energie Atomique | Détecteur de rayonnement électromagnétique et son procédé de fabrication. |
-
2004
- 2004-10-13 WO PCT/FR2004/002603 patent/WO2006040419A1/fr active Application Filing
- 2004-10-13 JP JP2007536207A patent/JP4638501B2/ja not_active Expired - Fee Related
- 2004-10-13 US US11/576,056 patent/US7759261B2/en not_active Expired - Fee Related
- 2004-10-13 EP EP04791517A patent/EP1800338A1/fr not_active Withdrawn
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4963389A (en) * | 1985-02-22 | 1990-10-16 | Mitsubishi Denki Kabushiki Kaisha | Method for producing hybrid integrated circuit substrate |
JPH05175629A (ja) * | 1991-12-24 | 1993-07-13 | Mitsubishi Electric Corp | 混成集積回路装置 |
US5661343A (en) * | 1994-03-16 | 1997-08-26 | Hitachi, Ltd. | Power hybrid integrated circuit apparatus |
FR2858716A1 (fr) * | 1997-11-20 | 2005-02-11 | Commissariat Energie Atomique | Procede d'obtention de couches localisees sur un circuit hybride |
US6467674B1 (en) * | 1999-12-09 | 2002-10-22 | Casio Computer Co., Ltd. | Method of manufacturing semiconductor device having sealing film on its surface |
Non-Patent Citations (1)
Title |
---|
PATENT ABSTRACTS OF JAPAN vol. 017, no. 583 (E - 1452) 22 October 1993 (1993-10-22) * |
Also Published As
Publication number | Publication date |
---|---|
US20080045037A1 (en) | 2008-02-21 |
US7759261B2 (en) | 2010-07-20 |
JP2008516458A (ja) | 2008-05-15 |
EP1800338A1 (fr) | 2007-06-27 |
JP4638501B2 (ja) | 2011-02-23 |
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