KR100387693B1 - 매립배선형성방법 - Google Patents

매립배선형성방법 Download PDF

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Publication number
KR100387693B1
KR100387693B1 KR1019960052591A KR19960052591A KR100387693B1 KR 100387693 B1 KR100387693 B1 KR 100387693B1 KR 1019960052591 A KR1019960052591 A KR 1019960052591A KR 19960052591 A KR19960052591 A KR 19960052591A KR 100387693 B1 KR100387693 B1 KR 100387693B1
Authority
KR
South Korea
Prior art keywords
film
forming
conductive film
copper
tungsten
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
KR1019960052591A
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English (en)
Korean (ko)
Other versions
KR970030369A (ko
Inventor
도쿠히코 다마키
Original Assignee
마츠시타 덴끼 산교 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication of KR970030369A publication Critical patent/KR970030369A/ko
Application granted granted Critical
Publication of KR100387693B1 publication Critical patent/KR100387693B1/ko
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/047—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein
    • H10W20/048—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein by using plasmas or gaseous environments, e.g. by nitriding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H10W20/059—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by reflowing or applying pressure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/32—Processing objects by plasma generation
    • H01J2237/33—Processing objects by plasma generation characterised by the type of processing
    • H01J2237/338—Changing chemical properties of treated surfaces
    • H01J2237/3387—Nitriding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/909—Controlled atmosphere
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Electrodes Of Semiconductors (AREA)
KR1019960052591A 1995-11-10 1996-11-07 매립배선형성방법 Expired - Lifetime KR100387693B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP29297495 1995-11-10
JP95-292974 1995-11-10

Publications (2)

Publication Number Publication Date
KR970030369A KR970030369A (ko) 1997-06-26
KR100387693B1 true KR100387693B1 (ko) 2003-10-04

Family

ID=17788842

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960052591A Expired - Lifetime KR100387693B1 (ko) 1995-11-10 1996-11-07 매립배선형성방법

Country Status (3)

Country Link
US (2) US6260266B1 (enExample)
KR (1) KR100387693B1 (enExample)
TW (1) TW310461B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100451493B1 (ko) * 1998-09-02 2004-12-04 주식회사 하이닉스반도체 반도체소자의금속배선형성방법

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JP4307592B2 (ja) * 1998-07-07 2009-08-05 Ｏｋｉセミコンダクタ株式会社 半導体素子における配線形成方法
KR100330163B1 (ko) * 2000-01-06 2002-03-28 윤종용 반도체 장치의 텅스텐 콘택 플러그 형성 방법
US6486063B2 (en) * 2000-03-02 2002-11-26 Tokyo Electron Limited Semiconductor device manufacturing method for a copper connection
GB0024294D0 (en) * 2000-10-04 2000-11-15 Univ Cambridge Tech Solid state embossing of polymer devices
US6613667B1 (en) * 2001-05-02 2003-09-02 The Texas A&M University System Forming an interconnect of a semiconductor device
US20030183943A1 (en) * 2002-03-28 2003-10-02 Swan Johanna M. Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
US6908845B2 (en) * 2002-03-28 2005-06-21 Intel Corporation Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
US6848177B2 (en) * 2002-03-28 2005-02-01 Intel Corporation Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
US7229918B2 (en) * 2005-02-14 2007-06-12 Infineon Technologies Ag Nitrogen rich barrier layers and methods of fabrication thereof
JP4441658B1 (ja) * 2008-12-19 2010-03-31 国立大学法人東北大学 銅配線形成方法、銅配線および半導体装置
US12444651B2 (en) 2009-08-04 2025-10-14 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US8207062B2 (en) * 2009-09-09 2012-06-26 Novellus Systems, Inc. Method for improving adhesion of low resistivity tungsten/tungsten nitride layers
JP6273257B2 (ja) 2012-03-27 2018-01-31 ノベラス・システムズ・インコーポレーテッドＮｏｖｅｌｌｕｓ Ｓｙｓｔｅｍｓ Ｉｎｃｏｒｐｏｒａｔｅｄ タングステンによるフィーチャ充填
US9012336B2 (en) * 2013-04-08 2015-04-21 Applied Materials, Inc. Method for conformal treatment of dielectric films using inductively coupled plasma
US9953857B2 (en) 2014-11-20 2018-04-24 International Business Machines Corporation Semiconductor device with buried local interconnects
US9953984B2 (en) 2015-02-11 2018-04-24 Lam Research Corporation Tungsten for wordline applications
US9978605B2 (en) 2015-05-27 2018-05-22 Lam Research Corporation Method of forming low resistivity fluorine free tungsten film without nucleation
US9754824B2 (en) 2015-05-27 2017-09-05 Lam Research Corporation Tungsten films having low fluorine content
JP7609636B2 (ja) 2017-08-14 2025-01-07 ラム リサーチ コーポレーション ３次元垂直ｎａｎｄワード線用の金属充填プロセス
JP2021523292A (ja) 2018-05-03 2021-09-02 ラム リサーチ コーポレーションＬａｍ Ｒｅｓｅａｒｃｈ Ｃｏｒｐｏｒａｔｉｏｎ ３ｄ ｎａｎｄ構造内にタングステンおよび他の金属を堆積させる方法
WO2020123987A1 (en) 2018-12-14 2020-06-18 Lam Research Corporation Atomic layer deposition on 3d nand structures
KR20200101717A (ko) * 2019-02-20 2020-08-28 에스케이하이닉스 주식회사 반도체장치 및 그 제조 방법
SG11202111277UA (en) 2019-04-11 2021-11-29 Lam Res Corp High step coverage tungsten deposition
CN113874545A (zh) 2019-05-22 2021-12-31 朗姆研究公司 无成核的钨沉积
US12077858B2 (en) 2019-08-12 2024-09-03 Lam Research Corporation Tungsten deposition
US12027419B2 (en) * 2020-06-25 2024-07-02 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device including liner structure

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US4277321A (en) * 1979-04-23 1981-07-07 Bell Telephone Laboratories, Incorporated Treating multilayer printed wiring boards
US4230553A (en) * 1979-04-23 1980-10-28 Bell Telephone Laboratories, Incorporated Treating multilayer printed wiring boards
US4762728A (en) * 1985-04-09 1988-08-09 Fairchild Semiconductor Corporation Low temperature plasma nitridation process and applications of nitride films formed thereby
JP2776826B2 (ja) * 1988-04-15 1998-07-16 株式会社日立製作所 半導体装置およびその製造方法
JP2714847B2 (ja) 1989-03-15 1998-02-16 富士通株式会社 半導体装置の製造方法
DE69025252T2 (de) * 1989-09-26 1996-07-04 Canon Kk Verfahren zum Herstellen einer abgeschiedenen Schicht und Verfahren zum Herstellen einer Halbleitervorrichtung
JPH03132022A (ja) 1989-10-18 1991-06-05 Hitachi Ltd 半導体装置の製造方法およびその装置
JP3132022B2 (ja) 1991-02-22 2001-02-05 スズキ株式会社 内燃機関のシリンダヘッド構造
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KR0124644B1 (ko) * 1994-05-10 1997-12-11 문정환 반도체소자의 다층금속배선의 형성방법
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Publication number Priority date Publication date Assignee Title
KR100451493B1 (ko) * 1998-09-02 2004-12-04 주식회사 하이닉스반도체 반도체소자의금속배선형성방법

Also Published As

Publication number Publication date
US20010029667A1 (en) 2001-10-18
US6664178B2 (en) 2003-12-16
KR970030369A (ko) 1997-06-26
TW310461B (enExample) 1997-07-11
US6260266B1 (en) 2001-07-17

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