KR100268629B1 - 반도체장치 - Google Patents

반도체장치 Download PDF

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Publication number
KR100268629B1
KR100268629B1 KR1019980015909A KR19980015909A KR100268629B1 KR 100268629 B1 KR100268629 B1 KR 100268629B1 KR 1019980015909 A KR1019980015909 A KR 1019980015909A KR 19980015909 A KR19980015909 A KR 19980015909A KR 100268629 B1 KR100268629 B1 KR 100268629B1
Authority
KR
South Korea
Prior art keywords
conductive layer
interlayer insulating
layer
insulating film
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
KR1019980015909A
Other languages
English (en)
Korean (ko)
Other versions
KR19990044725A (ko
Inventor
도모하루 마메타니
유키히로 나가이
Original Assignee
다니구찌 이찌로오, 기타오카 다카시
미쓰비시덴키 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 다니구찌 이찌로오, 기타오카 다카시, 미쓰비시덴키 가부시키가이샤 filed Critical 다니구찌 이찌로오, 기타오카 다카시
Publication of KR19990044725A publication Critical patent/KR19990044725A/ko
Application granted granted Critical
Publication of KR100268629B1 publication Critical patent/KR100268629B1/ko
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1019980015909A 1997-11-21 1998-05-04 반도체장치 Expired - Lifetime KR100268629B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP97-320850 1997-11-21
JP9320850A JPH11154701A (ja) 1997-11-21 1997-11-21 半導体装置

Publications (2)

Publication Number Publication Date
KR19990044725A KR19990044725A (ko) 1999-06-25
KR100268629B1 true KR100268629B1 (ko) 2000-10-16

Family

ID=18125952

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019980015909A Expired - Lifetime KR100268629B1 (ko) 1997-11-21 1998-05-04 반도체장치

Country Status (6)

Country Link
US (1) US6175156B1 (https=)
JP (1) JPH11154701A (https=)
KR (1) KR100268629B1 (https=)
CN (1) CN1149671C (https=)
DE (1) DE19813741B4 (https=)
TW (1) TW366519B (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6545359B1 (en) * 1998-12-18 2003-04-08 Semiconductor Energy Laboratory Co., Ltd. Wiring line and manufacture process thereof, and semiconductor device and manufacturing process thereof
US6965165B2 (en) 1998-12-21 2005-11-15 Mou-Shiung Lin Top layers of metal for high performance IC's
JP2003031657A (ja) * 2001-07-18 2003-01-31 Mitsubishi Electric Corp 半導体装置およびその製造方法
CN100342526C (zh) * 2003-08-22 2007-10-10 全懋精密科技股份有限公司 有电性连接垫金属保护层的半导体封装基板结构及其制法
JP2005252027A (ja) * 2004-03-04 2005-09-15 Nec Electronics Corp 多層配線構造の半導体装置
JP2008060532A (ja) * 2006-08-04 2008-03-13 Seiko Epson Corp 半導体装置
US8264077B2 (en) * 2008-12-29 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Backside metal of redistribution line with silicide layer on through-silicon via of semiconductor chips

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4834686A (https=) * 1971-09-09 1973-05-21
US4648937A (en) * 1985-10-30 1987-03-10 International Business Machines Corporation Method of preventing asymmetric etching of lines in sub-micrometer range sidewall images transfer
KR900003618B1 (ko) * 1986-05-30 1990-05-26 후지쓰가부시끼가이샤 반도체장치 및 그 제조방법
JP2546297B2 (ja) * 1987-11-02 1996-10-23 日本電気株式会社 半導体記憶装置
US5027185A (en) * 1988-06-06 1991-06-25 Industrial Technology Research Institute Polycide gate FET with salicide
JPH02222148A (ja) * 1989-02-22 1990-09-04 Yamaha Corp 半導体装置
DE69123175T2 (de) * 1990-05-31 1997-04-03 Canon Kk Verfahren zur Verdrahtung einer Halbleiterschaltung
JPH06326106A (ja) * 1993-03-18 1994-11-25 Sony Corp ダミーパターンの形成方法
JP2955459B2 (ja) * 1993-12-20 1999-10-04 株式会社東芝 半導体装置の製造方法
JPH08293523A (ja) * 1995-02-21 1996-11-05 Seiko Epson Corp 半導体装置およびその製造方法
US6015326A (en) * 1996-09-03 2000-01-18 Advanced Vision Technologies,Inc. Fabrication process for electron field-emission display

Also Published As

Publication number Publication date
DE19813741B4 (de) 2005-09-22
DE19813741A1 (de) 1999-06-02
HK1019118A1 (en) 2000-01-21
TW366519B (en) 1999-08-11
US6175156B1 (en) 2001-01-16
JPH11154701A (ja) 1999-06-08
CN1218291A (zh) 1999-06-02
CN1149671C (zh) 2004-05-12
KR19990044725A (ko) 1999-06-25

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