JPWO2020123587A5 - - Google Patents

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Publication number
JPWO2020123587A5
JPWO2020123587A5 JP2021533735A JP2021533735A JPWO2020123587A5 JP WO2020123587 A5 JPWO2020123587 A5 JP WO2020123587A5 JP 2021533735 A JP2021533735 A JP 2021533735A JP 2021533735 A JP2021533735 A JP 2021533735A JP WO2020123587 A5 JPWO2020123587 A5 JP WO2020123587A5
Authority
JP
Japan
Prior art keywords
output
input
coupled
integrator
offset detector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2021533735A
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English (en)
Japanese (ja)
Other versions
JP2022514233A5 (https=
JP2022514233A (ja
Publication date
Priority claimed from US16/219,067 external-priority patent/US10924123B2/en
Application filed filed Critical
Publication of JP2022514233A publication Critical patent/JP2022514233A/ja
Publication of JP2022514233A5 publication Critical patent/JP2022514233A5/ja
Publication of JPWO2020123587A5 publication Critical patent/JPWO2020123587A5/ja
Pending legal-status Critical Current

Links

JP2021533735A 2018-12-13 2019-12-11 直接フィードフォワード回路を備える位相同期ループ（ｐｌｌ） Pending JP2022514233A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/219,067 US10924123B2 (en) 2018-12-13 2018-12-13 Phase-locked loop (PLL) with direct feedforward circuit
US16/219,067 2018-12-13
PCT/US2019/065611 WO2020123587A1 (en) 2018-12-13 2019-12-11 Phase-locked loop (pll) with direct feedforward circuit

Publications (3)

Publication Number Publication Date
JP2022514233A JP2022514233A (ja) 2022-02-10
JP2022514233A5 JP2022514233A5 (https=) 2022-12-12
JPWO2020123587A5 true JPWO2020123587A5 (https=) 2022-12-12

Family

ID=71073070

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2021533735A Pending JP2022514233A (ja) 2018-12-13 2019-12-11 直接フィードフォワード回路を備える位相同期ループ（ｐｌｌ）

Country Status (6)

Country Link
US (4) US10924123B2 (https=)
EP (1) EP3895319B1 (https=)
JP (1) JP2022514233A (https=)
KR (1) KR20210102252A (https=)
CN (2) CN119853675A (https=)
WO (1) WO2020123587A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10924123B2 (en) 2018-12-13 2021-02-16 Texas Instruments Incorporated Phase-locked loop (PLL) with direct feedforward circuit
US11095293B1 (en) * 2020-12-31 2021-08-17 Texas Instruments Incorporated Low-power fractional analog PLL without feedback divider
US11558057B1 (en) 2021-11-04 2023-01-17 International Business Machines Corporation Phase locked loop pulse truncation

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4305045A (en) 1979-11-14 1981-12-08 Bell Telephone Laboratories, Incorporated Phase locked loop clock synchronizing circuit with programmable controller
JP2778421B2 (ja) * 1993-09-07 1998-07-23 日本電気株式会社 チャージポンプ型位相同期ループ
US5663685A (en) * 1996-03-29 1997-09-02 Bull Hn Information Systems Inc. Dual flip-flop detector type phase locked loop incorporating dynamic phase offset correction
WO2002005428A2 (en) * 2000-07-10 2002-01-17 Silicon Laboratories, Inc. Digitally-synthesized loop filter circuit particularly useful for a phase locked loop
US20020176188A1 (en) * 2001-05-25 2002-11-28 Infineon Technologies N.A. Inc. Offset cancellation of charge pump based phase detector
US6529084B1 (en) 2001-10-11 2003-03-04 International Business Machines Corporation Interleaved feedforward VCO and PLL
JP4220828B2 (ja) * 2003-04-25 2009-02-04 パナソニック株式会社 低域ろ波回路、フィードバックシステムおよび半導体集積回路
DE60314415T2 (de) * 2003-08-29 2008-02-21 Texas Instruments Inc., Dallas Phasenregelschleife mit einer Ladungspumpe und Störunterdrückungsverbesserung der Stromversorgung
KR100568538B1 (ko) * 2004-04-09 2006-04-07 삼성전자주식회사 자기 바이어스 위상 동기 루프
JP3939715B2 (ja) * 2004-08-20 2007-07-04 日本テキサス・インスツルメンツ株式会社 位相同期ループ回路
US7345550B2 (en) * 2005-12-05 2008-03-18 Sirific Wireless Corporation Type II phase locked loop using dual path and dual varactors to reduce loop filter components
US7548123B2 (en) * 2007-07-13 2009-06-16 Silicon Laboratories Inc. Dividerless PLL architecture
US8854094B2 (en) * 2008-03-21 2014-10-07 Broadcom Corporation Phase locked loop
JP5738749B2 (ja) * 2011-12-15 2015-06-24 ルネサスエレクトロニクス株式会社 Ｐｌｌ回路
US8487677B1 (en) * 2012-03-30 2013-07-16 Freescale Semiconductor, Inc. Phase locked loop with adaptive biasing
US9094028B2 (en) 2012-04-11 2015-07-28 Rambus Inc. Wide range frequency synthesizer with quadrature generation and spur cancellation
KR101904749B1 (ko) 2012-05-10 2018-10-08 삼성전자주식회사 위상 고정 루프의 스위칭 및 위상 잡음 향상 기법을 적용한 트랜시버
JP6148953B2 (ja) * 2013-09-26 2017-06-14 日本電波工業株式会社 Ｐｌｌ回路
US10924123B2 (en) * 2018-12-13 2021-02-16 Texas Instruments Incorporated Phase-locked loop (PLL) with direct feedforward circuit

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