JPWO2018070263A1 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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Abstract
Description
しかし、半導体基板を機械加工により研削した際の異物介在による、半導体基板と金属薄膜間の電気抵抗上昇や、半導体基板の研削時に発生した結晶欠陥によりチップ強度が低下し、モジュール基板への実装時や通電による負荷印加時にチップが破損するという問題があった。
図1は、この発明の実施の形態1による半導体装置の製造方法により製造された半導体装置の主要部のセル構造を示す断面図である。セル構造101は、SiC半導体装置であるSiC−MOSFETのプレーナーゲート構造である。図1に示すように、セル構造101は、n型のSiC基板1の上方側に位置する第1の主面(以下、表面とする)上に、n型のSiCからなる第1ドリフト層2を、第1層目のエピタキシャル膜として形成されており、第1ドリフト層2の表面には、第2ドリフト層3が第2層目のエピタキシャル膜として形成されている。第2ドリフト層3の表面には、活性化した一対のp型のベース領域4aが形成され、一対のp型のベース領域4a表面の一部にはそれぞれにはさらに、活性化したn型のソース領域5aが形成されている。そして、一対のベース領域4a及び一対のソース領域5aが同電極7の両端部の下方に位置し、一対のベース領域4a間に位置する第2ドリフト層3の一部分がゲート電極7の中央直下に位置するようにゲート電極7がゲート絶縁膜6で覆われるように形成されている。このように、SiC基板1の表面には、第1ドリフト層2、第2ドリフト層3、ベース領域4a、ソース領域5a、ゲート絶縁膜6、およびゲート電極7からなる能動領域が形成されている。さらに、一対のソース領域5aとゲート絶縁膜6で覆われたゲート電極7をさらに覆うようにソース電極8が形成されている。一方、SiC基板1の下方側に位置する第2の主面(以下、裏面とする)には、所定の厚さだけ研削されたSiC基板1の裏面側に形成されたSiC基板・ドレイン電極接合領域9に第1の主電極であるドレイン電極10が形成されている。なお、実際のSiC半導体装置の全体構成は、図1に示したセル構成がその両端をそれぞれ線対称の軸として連続する構成である。
その後、層間絶縁膜の形成(ステップS307)として、図4(h)に示すように、層間絶縁膜6bの成膜およびパターニングを行う。
2次研削ステージにおいても、1次研削ステージと同じく、所定量の研削加工が行われる。
ソース電極8に用いる金属材料としては、表面側のワイヤリングやはんだ付けなどの接合方法に応じて、適宜選択することが可能である。
実施の形態1では、ドレイン電極を形成した後に、ソース電極を形成する工程を示したが、実施の形態2では、ドレイン電極を形成する前に、ソース電極を形成する場合について説明する。
Claims (5)
- SiC基板の表面側に能動領域を形成する工程と、
前記SiC基板の裏面側に、平均砥粒径が1μm以上、5μm以下の砥石で研削して電極接合領域を形成する工程と、
前記電極接合領域に第1の主電極を成膜する工程と、
前記第1の主電極と前記電極接合領域をレーザー照射により電気的に接続する工程と、
前記レーザー照射された第1の主電極上に第2の主電極を成膜する工程と
を含むことを特徴とする半導体装置の製造方法。 - 前記第1の主電極と前記電極接合領域を前記レーザー照射により電気的に接続する際に用いるレーザーの照射エネルギーが、0.5J/cm2以上、3.0J/cm2以下であることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第1の主電極は、10nm以上、200nm以下の厚さであることを特徴とする請求項1または請求項2に記載の半導体装置の製造方法。
- 前記第2の主電極は、前記第1の主電極の10倍以上、50倍以下の厚さであることを特徴とする請求項1から請求項3のいずれか1項に記載の半導体装置の製造方法。
- 前記第1の主電極および前記第2の主電極は、ニッケルからなることを特徴とする請求項1から請求項4のいずれか1項に記載の半導体装置の製造方法。
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US10665459B2 (en) | 2020-05-26 |
DE112017005206T5 (de) | 2019-07-04 |
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