JPWO2012086107A1 - 電子部品実装構造中間体、電子部品実装構造体および電子部品実装構造体の製造方法 - Google Patents
電子部品実装構造中間体、電子部品実装構造体および電子部品実装構造体の製造方法 Download PDFInfo
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- JPWO2012086107A1 JPWO2012086107A1 JP2012549600A JP2012549600A JPWO2012086107A1 JP WO2012086107 A1 JPWO2012086107 A1 JP WO2012086107A1 JP 2012549600 A JP2012549600 A JP 2012549600A JP 2012549600 A JP2012549600 A JP 2012549600A JP WO2012086107 A1 JPWO2012086107 A1 JP WO2012086107A1
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
片面に第1の接続端子を有する第1の半導体チップと、
前記第1の半導体チップの前記片面に対向する面に第2の接続端子を有する第2の半導体チップと、
少なくとも片面に第3の接続端子を有し、前記第1の半導体チップおよび前記第2の半導体チップの間に配置されたフィルム配線基板とを備え、
前記第1の接続端子の少なくとも一部は、前記第2の接続端子の少なくとも一部と接続され、
前記第3の接続端子は、前記第1の接続端子の他の一部および前記第2の接続端子の他の一部のうち少なくともいずれかと接続されている、電子部品実装構造中間体である。
前記フィルム配線基板には、前記第1の半導体チップおよび前記第2の半導体チップのいずれの端部よりも外側へ出ている部分があり、
前記外側へ出ている部分の先端部には、配線によって前記第3の接続端子に接続された第4の接続端子が設けられている、第1の本発明の電子部品実装構造中間体である。
前記フィルム配線基板は可撓性を有する、第2の本発明の電子部品実装構造中間体である。
前記フィルム配線基板には、孔部が設けられており、
前記第1の接続端子の少なくとも一部と、前記第2の接続端子の少なくとも一部とは、前記孔部を介して接続されている、第2の本発明の電子部品実装構造中間体である。
前記フィルム配線基板の外縁部の少なくとも1箇所には、切り欠きがある、第2の本発明の電子部品実装構造中間体である。
前記フィルム配線基板は、複数の個片に分かれている、第2の本発明の電子部品実装構造中間体である。
前記第1の半導体チップおよび前記第2の半導体チップは、相対して配置されており、前記第1の半導体チップおよび前記第2の半導体チップの相対する各辺の長さの差は、±5%以内である、第2の本発明の電子部品実装構造中間体である。
第2〜第7のいずれかの本発明の電子部品実装構造中間体と、
第5の接続端子を有し、前記第1の半導体チップの他の片面が対面するように前記電子部品実装構造中間体が搭載されるチップ搭載基板とを備え、
前記第5の接続端子が、前記フィルム配線基板の前記第4の接続端子に接続されている、電子部品実装構造体である。
前記チップ搭載基板には、凹部が形成されており、
前記電子部品実装構造中間体は、前記第1の半導体チップが前記凹部に嵌るように、前記チップ搭載基板に搭載されている、第8の本発明の電子部品実装構造体である。
片面に第1の接続端子が形成された第1の半導体チップを、前記第1の接続端子が形成されていない面が対面するようにチップ搭載基板上に搭載する半導体チップ搭載工程と、
前記第1の半導体チップの前記第1の接続端子の一部と、フィルム配線基板の片面に形成された第3の接続端子とを電気的に接続する第1の端子接続工程と、
前記第1の半導体チップの前記フィルム配線基板を接続した側から、片面に第2の接続端子が形成された第2の半導体チップを重ね合わせて積層し、前記第3の接続端子に接続されていない前記第1の接続端子と、前記第2の接続端子とを電気的に接続する第2の端子接続工程と、
前記フィルム配線基板の、前記第1の半導体チップおよび前記第2の半導体チップのいずれの端部よりも外側へ出ている部分の先端部分に形成され、前記第3の接続端子に接続されている第4の接続端子を、前記チップ搭載基板上に形成されている第5の接続端子に電気的に接続する第3の端子接続工程とを備えた、電子部品実装構造体の製造方法である。
前記第1の端子接続工程、前記第2の端子接続工程、前記半導体チップ搭載工程、前記第3の端子接続工程の順に処理する、第10の本発明の電子部品実装構造体の製造方法である。
前記第1の端子接続工程、前記半導体チップ搭載工程、前記第3の端子接続工程、前記第2の端子接続工程の順に処理する、第10の本発明の電子部品実装構造体の製造方法である。
前記半導体チップ搭載工程、前記第1の端子接続工程、前記第2の端子接続工程、前記第3の端子接続工程の順に処理する、第10の本発明の電子部品実装構造体の製造方法である。
図1(a)は、本発明の第1の実施の形態にかかる電子部品実装構造体の構成を示す断面図であり、図1(b)は、本実施の形態にかかる電子部品実装構造体の構成を示す平面図である。図1(a)は、図1(b)のA−A間の断面を示している。
図5(a)〜(f)は、本発明の第2の実施の形態にかかる電子部品実装構造体の形成工程を示す断面図である。
図6は、本発明の第3の実施の形態にかかる電子部品実装構造体の構成を示す断面図である。
図7は、本発明の第4の実施の形態にかかる電子部品実装構造体の構成を示す断面図である。
図8は、本発明の第5の実施の形態にかかる電子部品実装構造体の構成を示す断面図である。
図9は、本発明の第6の実施の形態にかかる電子部品実装構造体の構成を示す断面図である。
2、3、7、7a、7b、10、13、14、16、16a、16b、44、57 接続端子群
4、5、11、17、18、45 突起電極
6、6a、6b、26、56 フィルム配線層
8、23、24、34、40、43、52、54、55 フィルム配線基板
9、29、33、42、51 半導体メモリチップ
12、32、41、53 樹脂基板
15 スルーホール
19 くりぬき孔
20 切り欠き
46 ビアホール
60、61、62、63 電子部品実装構造中間体
91 ワイヤ
101 第1平面
102 第2平面
103 第3平面
104 第4平面
105 第5平面
106 第6平面
110 窪み部
Claims (13)
- 片面に第1の接続端子を有する第1の半導体チップと、
前記第1の半導体チップの前記片面に対向する面に第2の接続端子を有する第2の半導体チップと、
少なくとも片面に第3の接続端子を有し、前記第1の半導体チップおよび前記第2の半導体チップの間に配置されたフィルム配線基板とを備え、
前記第1の接続端子の少なくとも一部は、前記第2の接続端子の少なくとも一部と接続され、
前記第3の接続端子は、前記第1の接続端子の他の一部および前記第2の接続端子の他の一部のうち少なくともいずれかと接続されている、電子部品実装構造中間体。 - 前記フィルム配線基板には、前記第1の半導体チップおよび前記第2の半導体チップのいずれの端部よりも外側へ出ている部分があり、
前記外側へ出ている部分の先端部には、配線によって前記第3の接続端子に接続された第4の接続端子が設けられている、請求項1に記載の電子部品実装構造中間体。 - 前記フィルム配線基板は可撓性を有する、請求項2に記載の電子部品実装構造中間体。
- 前記フィルム配線基板には、孔部が設けられており、
前記第1の接続端子の少なくとも一部と、前記第2の接続端子の少なくとも一部とは、前記孔部を介して接続されている、請求項2に記載の電子部品実装構造中間体。 - 前記フィルム配線基板の外縁部の少なくとも1箇所には、切り欠きがある、請求項2に記載の電子部品実装構造中間体。
- 前記フィルム配線基板は、複数の個片に分かれている、請求項2に記載の電子部品実装構造中間体。
- 前記第1の半導体チップおよび前記第2の半導体チップは、相対して配置されており、前記第1の半導体チップおよび前記第2の半導体チップの相対する各辺の長さの差は、±5%以内である、請求項2に記載の電子部品実装構造中間体。
- 請求項2〜7のいずれかに記載の電子部品実装構造中間体と、
第5の接続端子を有し、前記第1の半導体チップの他の片面が対面するように前記電子部品実装構造中間体が搭載されるチップ搭載基板とを備え、
前記第5の接続端子が、前記フィルム配線基板の前記第4の接続端子に接続されている、電子部品実装構造体。 - 前記チップ搭載基板には、凹部が形成されており、
前記電子部品実装構造中間体は、前記第1の半導体チップが前記凹部に嵌るように、前記チップ搭載基板に搭載されている、請求項8に記載の電子部品実装構造体。 - 片面に第1の接続端子が形成された第1の半導体チップを、前記第1の接続端子が形成されていない面が対面するようにチップ搭載基板上に搭載する半導体チップ搭載工程と、
前記第1の半導体チップの前記第1の接続端子の一部と、フィルム配線基板の片面に形成された第3の接続端子とを電気的に接続する第1の端子接続工程と、
前記第1の半導体チップの前記フィルム配線基板を接続した側から、片面に第2の接続端子が形成された第2の半導体チップを重ね合わせて積層し、前記第3の接続端子に接続されていない前記第1の接続端子と、前記第2の接続端子とを電気的に接続する第2の端子接続工程と、
前記フィルム配線基板の、前記第1の半導体チップおよび前記第2の半導体チップのいずれの端部よりも外側へ出ている部分の先端部分に形成され、前記第3の接続端子に接続されている第4の接続端子を、前記チップ搭載基板上に形成されている第5の接続端子に電気的に接続する第3の端子接続工程とを備えた、電子部品実装構造体の製造方法。 - 前記第1の端子接続工程、前記第2の端子接続工程、前記半導体チップ搭載工程、前記第3の端子接続工程の順に処理する、請求項10に記載の電子部品実装構造体の製造方法。
- 前記第1の端子接続工程、前記半導体チップ搭載工程、前記第3の端子接続工程、前記第2の端子接続工程の順に処理する、請求項10に記載の電子部品実装構造体の製造方法。
- 前記半導体チップ搭載工程、前記第1の端子接続工程、前記第2の端子接続工程、前記第3の端子接続工程の順に処理する、請求項10に記載の電子部品実装構造体の製造方法。
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