JPWO2009088000A1 - 配線基板、半導体装置及びそれらの製造方法 - Google Patents
配線基板、半導体装置及びそれらの製造方法 Download PDFInfo
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- JPWO2009088000A1 JPWO2009088000A1 JP2009548919A JP2009548919A JPWO2009088000A1 JP WO2009088000 A1 JPWO2009088000 A1 JP WO2009088000A1 JP 2009548919 A JP2009548919 A JP 2009548919A JP 2009548919 A JP2009548919 A JP 2009548919A JP WO2009088000 A1 JPWO2009088000 A1 JP WO2009088000A1
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- layer
- insulating layer
- wiring
- terminal
- wiring board
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
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- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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Abstract
Description
本発明は、日本国特許出願:特願2008−002341号(2008年1月9日出願)の優先権主張に基づくものであり、同出願の全記載内容は引用をもって本書に組み込み記載されているものとする。
12 第1面
13 第2面
14 第1端子
15 第2端子(金属ポスト)
16 ランド(配線層)
17 配線層
18、18a、18b、18c 絶縁層
19 ビア(金属ポスト)
20 矯正領域
21 密着層(給電層)
22、22a、22b 半導体素子
23a、23b ハンダ
24a、24b アンダーフィル
25 ハンダボール
26 接着剤
27 ボンディングワイヤ
28 導電体膜
30 レジスト
31 モールド
32 応力集中領域
33 支持体
Claims (25)
- 絶縁層と配線層が交互に積層するとともに、前記配線層間がビアによって電気的に接続された配線基板であって、
第1面に設けられるとともに前記絶縁層に埋設された第1端子と、
前記第1面の反対側の第2面に設けられるとともに前記絶縁層に埋設された第2端子と、
前記絶縁層内に設けられるとともに前記第1端子に接触するランドと、
を備え、
前記ランドと、前記絶縁層を介して設けられる前記配線層との間を電気的に接続するビアは、前記ランド側の端部に接続界面が存在せず、前記配線層側の端部に接続界面が存在することを特徴とする配線基板。 - 前記配線層間を電気的に接続する前記ビアは、前記第2面側の端部にのみ接合界面が存在することを特徴とする請求項1記載の配線基板。
- 前記配線層の前記第1面側の面に前記配線層と前記絶縁層とを密着させる密着層を有することを特徴とする請求項1又は2記載の配線基板。
- 前記ランドの前記第1端子側の面に前記密着層を有することを特徴とする請求項3記載の配線基板。
- 前記第1端子は、前記第1面側に露出する表面積が、前記ランドと接触している面の断面積より小さく構成されていることを特徴とする請求項1乃至4のいずれか一に記載の配線基板。
- 前記第2端子は、前記配線層に直接設けられ、かつ、前記第2面側に露出する表面積が、前記配線層と接触している断面積より大きく構成されることを特徴とする請求項1乃至5のいずれか一に記載の配線基板。
- 前記絶縁層は、1種又は複数種の絶縁材料からなることを特徴とする請求項1乃至6のいずれか一に記載の配線基板。
- 前記絶縁層は、複数種の絶縁材料からなり、前記第1面と前記第2面の絶縁材料が同じであることを特徴とする請求項1乃至7のいずれか一に記載の配線基板。
- 前記第1端子及び前記第2端子は、複数の金属が積層された構成となっていることを特徴とする請求項1乃至8のいずれか一に記載の配線基板。
- 前記第2端子は、前記第2面側の前記絶縁層の表面より窪んでいることを特徴とする請求項1乃至9のいずれか一に記載の配線基板。
- 前記第2端子は、前記第2面側の前記絶縁層の表面より突出していることを特徴とする請求項1乃至9のいずれか一に記載の配線基板。
- 請求項1乃至11に記載の配線基板の片面又は両面に半導体素子を搭載したことを特徴とする半導体装置。
- 前記半導体素子と前記配線基板とが、フリップチップ接続又はワイヤーボンディング接続のいずれか又は両方により搭載されていることを特徴とする請求項12に記載の半導体装置。
- 請求項1乃至11に記載の配線基板の両面に半導体素子がフリップチップ接続され、かつ、両面に搭載された前記半導体素子の対向する電極間を前記配線基板内の前記ビアを積み上げることを主として結線していることを特徴とする半導体装置。
- 支持体上に開口部を有する第1絶縁層を形成する第1の工程と、
前記開口部内に第1端子を形成する第2の工程と、
前記第1絶縁層及び前記第1端子上に、配線層、及びビアとなる金属ポストを形成する第3の工程と、
前記第1絶縁層、前記配線層、及び前記金属ポスト上に第2絶縁層を形成した後、前記金属ポストが露出するまで前記第2絶縁層の表面を研磨する第4の工程と、
前記第2絶縁層上にて前記第3の工程と前記第4の工程を交互に繰り返して多層配線層を形成する第5の工程と、
前記支持体を除去する第6の工程と、
を含むことを特徴とする配線基板の製造方法。 - 前記第3の工程において、前記配線層及び前記金属ポストを形成する前に、前記第1絶縁層及び前記第1端子上に給電層を形成し、その後、前記給電層を用いて電解めっきにより前記配線層及び前記金属ポストを形成することを特徴とする請求項15記載の配線基板の製造方法。
- 前記第1の工程において、前記第1絶縁層を形成する前に、前記支持体上に導電体層を形成し、その後、前記導電体層上に前記第1絶縁層を形成し、
前記第6の工程において、前記支持体と前記導電体層の界面を剥離することを特徴とする請求項15又は16記載の配線基板の製造方法。 - 前記第5の工程の後に、最表面に第3絶縁層を形成する第7の工程を含むことを特徴とする請求項15乃至17のいずれか一に記載の配線基板の製造方法。
- 前記第7の工程において、前記第3絶縁層に開口部を形成した後、前記開口部内に第2端子を形成することを特徴とする請求項18記載の配線基板の製造方法。
- 支持体上に開口部を有する第1絶縁層を形成する第1の工程と、
前記開口部内に第1端子を形成する第2の工程と、
前記第1絶縁層及び前記第1端子上に、配線層、及びビアとなる金属ポストを形成する第3の工程と、
前記第1絶縁層、前記配線層、及び前記金属ポスト上に第2絶縁層を形成した後、前記金属ポストが露出するまで前記第2絶縁層の表面を研磨する第4の工程と、
前記第2絶縁層上にて前記第3の工程と前記第4の工程を交互に繰り返して多層配線層を形成する第5の工程と、
半導体素子を搭載する第6の工程と、
前記支持体を除去する第7の工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記第6の工程と前記第7の工程の間に、前記半導体素子を搭載した面にモールド樹脂を形成する第8の工程を含むことを特徴とする請求項20記載の半導体装置の製造方法。
- 前記第1の工程において、前記第1絶縁層を形成する前に、前記支持体上に導電体層を形成し、その後、前記導電体層上に前記第1絶縁層を形成し、
前記第7の工程において、前記支持体と前記導電体層の界面を剥離することを特徴とする請求項20又は21記載の半導体装置の製造方法。 - 前記第7の工程の後に、露出した前記第1端子上に半導体素子を搭載する第9の工程を含むことを特徴とする請求項20乃至22のいずれか一に記載の半導体装置の製造方法。
- 前記第6の工程、及び前記第9の工程において、半導体素子がフリップチップ接続又はワイヤーボンディング接続のいずれかもしくは両方により搭載されることを特徴とする請求項20乃至23のいずれか一に記載の半導体装置の製造方法。
- 前記第7の工程の後に、外部端子としての半田ボールを搭載する第10の工程を含むことを特徴とする請求項20乃至24のいずれか一に記載の半導体装置の製造方法。
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