JPWO2005122276A1 - 半導体装置及びその製造方法 - Google Patents
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Abstract
Description
撓む前の梁の長さおよび梁の下部に設けられた前記空隙の深さの少なくとも一方が異なっていることで異なる歪みが導入されている少なくとも2種のFinFETを有する上記7記載の半導体装置。
撓んだ梁の長さ=2Rtan−1(L/2/(R−d))
このモデルに基づくと、例えば歪み1%を実現するには、L=320nm、d=20nmとすればよく、歪み0.5%を実現するには、L=460nm、d=20nmとすればよい。
[構造]
図1、図2に、本発明の第1の実施形態としての半導体装置の構造模式図を示す。図1(a)は上面図、図1(b)、(c)および(d)は、図1(a)のA−A’線、B−B’線、C−C’線にそれぞれ沿った断面図である。また、図2(a)は上面図、図2(b)、(c)および(d)は、図2(a)のA−A’線、B−B’線、C−C’線にそれぞれ沿った断面図である。図1は、ダブルゲート型のFinFETであり、シリサイド形成前の状態を示している。また図2は、トリプルゲート型のFinFETであり、シリサイド形成前の状態を示している。
次に、図1〜図10を参照して、第1の実施形態の製造方法を説明する。図3〜図10では、トリプルゲート型のFinFET(図2)の製造方法を説明するが、ダブルゲート型のFinFET(図1)でも、一部を除き同じである。その違いについては後述する。
本発明による方法では、集積回路を構成するFinFET1つ1つについて、異なる歪みを与えることが可能である。例えば、あるFinFETに歪みを与えず、従来型のFinFETとして用いようとすれば、図3の工程後、図4の埋め込み酸化膜エッチングでエッチングされないように、このFinFETをマスクしておけばよい。また、歪み量は、上記の通り、Lとdで制御できるので、d一定の条件では、Lを各FinFETで変えることで歪みを制御できる。またL一定の条件では、埋め込み酸化膜エッチングdの量を各FinFETで変える、すなわち埋め込み酸化膜エッチングを複数回行い、適宜FinFETをマスクしてやることで、各FinFETに異なる歪みを与えられる。また、これらの方法を組み合わせることも可能である。
次に、本発明の第2の実施形態について図面を参照して説明する。
次に、本発明の第3の実施形態について図面を参照して説明する。
次に、第4の実施形態について図面を参照して説明する。
次に、第5の実施形態について図面を参照して詳細に説明する。
次に、本発明の第6の実施形態について図面を参照して説明する。これまでの実施形態では、撓んだ梁を利用したFinFETについて説明したが、本実施形態では、撓んだ梁構造をプレーナー型のFETのチャネルに利用する例を示す。
Claims (12)
- 半導体で形成された撓んだ梁の中を電流が流れることを特徴とする半導体装置。
- 前記梁は両端が固定された両持ち梁構造であって、梁方向に引っ張り歪みが与えられていることを特徴とする請求項1記載の半導体装置。
- 前記梁をFETのチャネル領域として使用することを特徴とする請求項1または2記載の半導体装置。
- 前記FETはFinFETであって、前記梁の少なくとも側面部をチャネル領域として使用することを特徴とする請求項3記載の半導体装置。
- 前記FETはプレーナー型FETであって、前記梁の上面部をチャネル領域として使用することを特徴とする請求項3記載の半導体装置。
- 前記梁は、梁の下部に設けられた空隙の底に梁中央部が付着していることを特徴とする請求項2〜5のいずれかに記載の半導体装置。
- 前記梁の歪みが、撓む前の梁の長さと、梁の下部に設けられた前記空隙の深さとによって制御されている請求項6記載の半導体装置。
- 複数のFinFETを有する半導体装置であって、
撓む前の梁の長さおよび梁の下部に設けられた前記空隙の深さの少なくとも一方が異なっていることで異なる歪みが導入されている少なくとも2種のFinFETを有する請求項7記載の半導体装置。 - 半導体で形成された撓んだ梁の中を電流が流れる半導体装置の製造方法であって、
半導体で形成された両持ち梁構造の真っ直ぐな梁を、その下部に空隙を作ることで形成する工程と、
この空隙に液体を満たす工程と、
この液体を乾燥して梁の中央を前記空隙の底部に付着させて撓んだ梁を形成する工程とを有することを特徴とする半導体装置の製造方法。 - 前記液体が水または水銀であることを特徴とする請求項9記載の半導体装置の製造方法。
- 前記の両持ち梁構造の真っ直ぐな梁を形成する工程に先立ち、前記梁を構成する半導体からなる第1の層と、第1の層の下にあって第1の層とはエッチング速度の異なる材料からなる第2の層を有する基板を用意する工程を有し、
前記の両持ち梁構造の真っ直ぐな梁を形成する工程が、第2の層の少なくとも一部をエッチングして除去して、第1の層の下部の一部に空隙を形成する工程であることを特徴とする請求項9または10記載の半導体装置の製造方法。 - 基板上に埋め込み絶縁膜と半導体層が積層されたSOI基板を用意する工程と、
前記半導体層をパターニングして、所定幅を有するFinを形成する工程と、
このFin下の前記埋め込み絶縁膜をエッチングして、このFinの下部に空隙を形成して真っ直ぐな梁とする工程と、
この空隙に液体を満たす工程と、
この液体を乾燥しFinを空隙の底部に付着させて撓ませる工程と
を有することを特徴とするFinFETの製造方法。
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Families Citing this family (75)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6909151B2 (en) | 2003-06-27 | 2005-06-21 | Intel Corporation | Nonplanar device with stress incorporation layer and method of fabrication |
US7456476B2 (en) * | 2003-06-27 | 2008-11-25 | Intel Corporation | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication |
US7154118B2 (en) | 2004-03-31 | 2006-12-26 | Intel Corporation | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication |
US7042009B2 (en) | 2004-06-30 | 2006-05-09 | Intel Corporation | High mobility tri-gate devices and methods of fabrication |
US7348284B2 (en) | 2004-08-10 | 2008-03-25 | Intel Corporation | Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow |
US7422946B2 (en) | 2004-09-29 | 2008-09-09 | Intel Corporation | Independently accessed double-gate and tri-gate transistors in same process flow |
US20060086977A1 (en) | 2004-10-25 | 2006-04-27 | Uday Shah | Nonplanar device with thinned lower body portion and method of fabrication |
US7518196B2 (en) | 2005-02-23 | 2009-04-14 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US20060202266A1 (en) | 2005-03-14 | 2006-09-14 | Marko Radosavljevic | Field effect transistor with metal source/drain regions |
WO2006132172A1 (ja) | 2005-06-07 | 2006-12-14 | Nec Corporation | フィン型電界効果型トランジスタ、半導体装置及びその製造方法 |
US7858481B2 (en) | 2005-06-15 | 2010-12-28 | Intel Corporation | Method for fabricating transistor with thinned channel |
US7547637B2 (en) | 2005-06-21 | 2009-06-16 | Intel Corporation | Methods for patterning a semiconductor film |
US7279375B2 (en) * | 2005-06-30 | 2007-10-09 | Intel Corporation | Block contact architectures for nanoscale channel transistors |
US7402875B2 (en) | 2005-08-17 | 2008-07-22 | Intel Corporation | Lateral undercut of metal gate in SOI device |
US7479421B2 (en) | 2005-09-28 | 2009-01-20 | Intel Corporation | Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby |
US20070090416A1 (en) | 2005-09-28 | 2007-04-26 | Doyle Brian S | CMOS devices with a single work function gate electrode and method of fabrication |
US7485503B2 (en) | 2005-11-30 | 2009-02-03 | Intel Corporation | Dielectric interface for group III-V semiconductor device |
US8143646B2 (en) | 2006-08-02 | 2012-03-27 | Intel Corporation | Stacking fault and twin blocking barrier for integrating III-V on Si |
US7829407B2 (en) | 2006-11-20 | 2010-11-09 | International Business Machines Corporation | Method of fabricating a stressed MOSFET by bending SOI region |
US8319295B2 (en) * | 2007-01-10 | 2012-11-27 | Imec | Use of F-based gate etch to passivate the high-k/metal gate stack for deep submicron transistor technologies |
JPWO2009107562A1 (ja) * | 2008-02-29 | 2011-06-30 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
US8362566B2 (en) | 2008-06-23 | 2013-01-29 | Intel Corporation | Stress in trigate devices using complimentary gate fill materials |
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US8957482B2 (en) * | 2009-03-31 | 2015-02-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrical fuse and related applications |
US8912602B2 (en) | 2009-04-14 | 2014-12-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs and methods for forming the same |
US8461015B2 (en) * | 2009-07-08 | 2013-06-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | STI structure and method of forming bottom void in same |
US8497528B2 (en) | 2010-05-06 | 2013-07-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for fabricating a strained structure |
US9484462B2 (en) | 2009-09-24 | 2016-11-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin structure of fin field effect transistor |
US8759943B2 (en) | 2010-10-08 | 2014-06-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Transistor having notched fin structure and method of making the same |
US8482073B2 (en) | 2010-03-25 | 2013-07-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit including FINFETs and methods for forming the same |
US8629478B2 (en) | 2009-07-31 | 2014-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin structure for high mobility multiple-gate transistor |
US8440517B2 (en) | 2010-10-13 | 2013-05-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET and method of fabricating the same |
US8298925B2 (en) | 2010-11-08 | 2012-10-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming ultra shallow junction |
US8264021B2 (en) * | 2009-10-01 | 2012-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Finfets and methods for forming the same |
US8980719B2 (en) | 2010-04-28 | 2015-03-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for doping fin field-effect transistors |
US8264032B2 (en) | 2009-09-01 | 2012-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Accumulation type FinFET, circuits and fabrication method thereof |
US8187928B2 (en) | 2010-09-21 | 2012-05-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming integrated circuits |
US8472227B2 (en) | 2010-01-27 | 2013-06-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuits and methods for forming the same |
US8623728B2 (en) | 2009-07-28 | 2014-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming high germanium concentration SiGe stressor |
US20110097867A1 (en) * | 2009-10-22 | 2011-04-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of controlling gate thicknesses in forming fusi gates |
US8110466B2 (en) | 2009-10-27 | 2012-02-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cross OD FinFET patterning |
WO2011067821A1 (ja) * | 2009-12-04 | 2011-06-09 | 株式会社 東芝 | 半導体装置の製造方法 |
CN102104069B (zh) * | 2009-12-16 | 2012-11-21 | 中国科学院微电子研究所 | 鳍式晶体管结构及其制作方法 |
US8269209B2 (en) * | 2009-12-18 | 2012-09-18 | Intel Corporation | Isolation for nanowire devices |
CN102117829B (zh) * | 2009-12-30 | 2012-11-21 | 中国科学院微电子研究所 | 鳍式晶体管结构及其制作方法 |
US9040393B2 (en) | 2010-01-14 | 2015-05-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming semiconductor structure |
US9130058B2 (en) | 2010-07-26 | 2015-09-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Forming crown active regions for FinFETs |
US8603924B2 (en) | 2010-10-19 | 2013-12-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming gate dielectric material |
US9048181B2 (en) | 2010-11-08 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming ultra shallow junction |
US8769446B2 (en) | 2010-11-12 | 2014-07-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and device for increasing fin device density for unaligned fins |
US8889494B2 (en) | 2010-12-29 | 2014-11-18 | Globalfoundries Singapore Pte. Ltd. | Finfet |
US8492235B2 (en) | 2010-12-29 | 2013-07-23 | Globalfoundries Singapore Pte. Ltd. | FinFET with stressors |
US8592915B2 (en) | 2011-01-25 | 2013-11-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Doped oxide for shallow trench isolation (STI) |
US8877602B2 (en) | 2011-01-25 | 2014-11-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms of doping oxide for forming shallow trench isolation |
US8431453B2 (en) | 2011-03-31 | 2013-04-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Plasma doping to reduce dielectric loss during removal of dummy layers in a gate structure |
JP5562921B2 (ja) * | 2011-10-21 | 2014-07-30 | 株式会社東芝 | 半導体装置 |
US9048260B2 (en) | 2011-12-31 | 2015-06-02 | Intel Corporation | Method of forming a semiconductor device with tall fins and using hard mask etch stops |
US8659097B2 (en) | 2012-01-16 | 2014-02-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Control fin heights in FinFET structures |
JP5926086B2 (ja) * | 2012-03-28 | 2016-05-25 | 株式会社Screenホールディングス | 基板処理装置および基板処理方法 |
WO2014065343A1 (en) * | 2012-10-24 | 2014-05-01 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
US9000489B2 (en) * | 2012-10-31 | 2015-04-07 | International Business Machines Corporation | Local interconnects for field effect transistor devices |
US9224849B2 (en) * | 2012-12-28 | 2015-12-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Transistors with wrapped-around gates and methods for forming the same |
US9041125B2 (en) | 2013-03-11 | 2015-05-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin shape for fin field-effect transistors and method of forming |
US9029213B2 (en) * | 2013-05-10 | 2015-05-12 | International Business Machines Corporation | Stringer-free gate electrode for a suspended semiconductor fin |
US9006842B2 (en) | 2013-05-30 | 2015-04-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Tuning strain in semiconductor devices |
US9349850B2 (en) | 2013-07-17 | 2016-05-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thermally tuning strain in semiconductor devices |
US9318574B2 (en) | 2014-06-18 | 2016-04-19 | International Business Machines Corporation | Method and structure for enabling high aspect ratio sacrificial gates |
US9620417B2 (en) * | 2014-09-30 | 2017-04-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Apparatus and method of manufacturing fin-FET devices |
US9362311B1 (en) | 2015-07-24 | 2016-06-07 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor device |
US9524969B1 (en) * | 2015-07-29 | 2016-12-20 | International Business Machines Corporation | Integrated circuit having strained fins on bulk substrate |
US20170084454A1 (en) * | 2015-09-17 | 2017-03-23 | International Business Machines Corporation | Uniform height tall fins with varying silicon germanium concentrations |
CN107680955B (zh) * | 2016-08-02 | 2020-01-21 | 中芯国际集成电路制造(北京)有限公司 | 静电放电保护器件、半导体装置及制造方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001144276A (ja) * | 1999-08-31 | 2001-05-25 | Toshiba Corp | 半導体基板およびその製造方法 |
JP2004128185A (ja) * | 2002-10-02 | 2004-04-22 | Renesas Technology Corp | 絶縁ゲート型電界効果型トランジスタ及び半導体装置、並びにその製造方法 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3376211B2 (ja) | 1996-05-29 | 2003-02-10 | 株式会社東芝 | 半導体装置、半導体基板の製造方法及び半導体装置の製造方法 |
JP3389009B2 (ja) | 1996-07-02 | 2003-03-24 | 株式会社東芝 | 半導体装置およびその製造方法 |
JP2000277715A (ja) | 1999-03-25 | 2000-10-06 | Matsushita Electric Ind Co Ltd | 半導体基板,その製造方法及び半導体装置 |
US6567715B1 (en) * | 2000-04-19 | 2003-05-20 | Sandia Corporation | Method and system for automated on-chip material and structural certification of MEMS devices |
JP2002057329A (ja) | 2000-08-09 | 2002-02-22 | Toshiba Corp | 縦型電界効果トランジスタ及びその製造方法 |
KR100363332B1 (en) | 2001-05-23 | 2002-12-05 | Samsung Electronics Co Ltd | Method for forming semiconductor device having gate all-around type transistor |
JP3782021B2 (ja) | 2002-02-22 | 2006-06-07 | 株式会社東芝 | 半導体装置、半導体装置の製造方法、半導体基板の製造方法 |
JPWO2005022637A1 (ja) | 2003-08-28 | 2007-11-01 | 日本電気株式会社 | フィン型電界効果トランジスタを有する半導体装置 |
JP4004448B2 (ja) * | 2003-09-24 | 2007-11-07 | 富士通株式会社 | 半導体装置およびその製造方法 |
WO2005038931A1 (ja) | 2003-10-20 | 2005-04-28 | Nec Corporation | 半導体装置及び半導体装置の製造方法 |
WO2005091374A1 (ja) | 2004-03-19 | 2005-09-29 | Nec Corporation | 半導体装置及びその製造方法 |
JPWO2005122272A1 (ja) | 2004-06-08 | 2008-04-10 | 日本電気株式会社 | 歪みシリコンチャネル層を有するmis型電界効果トランジスタ |
JP5012023B2 (ja) | 2004-07-14 | 2012-08-29 | 日本電気株式会社 | 電界効果型トランジスタ及びその製造方法 |
US20090014795A1 (en) | 2004-07-29 | 2009-01-15 | Risho Koh | Substrate for field effect transistor, field effect transistor and method for production thereof |
US7125759B2 (en) * | 2005-03-23 | 2006-10-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor-on-insulator (SOI) strained active areas |
US7326601B2 (en) * | 2005-09-26 | 2008-02-05 | Advanced Micro Devices, Inc. | Methods for fabrication of a stressed MOS device |
-
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Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001144276A (ja) * | 1999-08-31 | 2001-05-25 | Toshiba Corp | 半導体基板およびその製造方法 |
JP2004128185A (ja) * | 2002-10-02 | 2004-04-22 | Renesas Technology Corp | 絶縁ゲート型電界効果型トランジスタ及び半導体装置、並びにその製造方法 |
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