JPS647503B2 - - Google Patents

Info

Publication number
JPS647503B2
JPS647503B2 JP54095560A JP9556079A JPS647503B2 JP S647503 B2 JPS647503 B2 JP S647503B2 JP 54095560 A JP54095560 A JP 54095560A JP 9556079 A JP9556079 A JP 9556079A JP S647503 B2 JPS647503 B2 JP S647503B2
Authority
JP
Japan
Prior art keywords
strip
etching
edge
composite
etch resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54095560A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5519900A (en
Inventor
Danieru Baanzu Kaamen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Publication of JPS5519900A publication Critical patent/JPS5519900A/ja
Publication of JPS647503B2 publication Critical patent/JPS647503B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4839—Assembly of a flat lead with an insulating support, e.g. for TAB
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4092—Integral conductive tabs, i.e. conductive parts partly detached from the substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor
    • Y10T156/1052—Methods of surface bonding and/or assembly therefor with cutting, punching, tearing or severing
    • Y10T156/1056—Perforating lamina
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP9556079A 1978-07-26 1979-07-26 Method of manufacturing composite tape with bump for automatically bonding semiconductor device Granted JPS5519900A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/921,643 US4209355A (en) 1978-07-26 1978-07-26 Manufacture of bumped composite tape for automatic gang bonding of semiconductor devices

Publications (2)

Publication Number Publication Date
JPS5519900A JPS5519900A (en) 1980-02-12
JPS647503B2 true JPS647503B2 (enExample) 1989-02-09

Family

ID=25445730

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9556079A Granted JPS5519900A (en) 1978-07-26 1979-07-26 Method of manufacturing composite tape with bump for automatically bonding semiconductor device

Country Status (6)

Country Link
US (1) US4209355A (enExample)
JP (1) JPS5519900A (enExample)
CA (1) CA1124407A (enExample)
DE (1) DE2926200A1 (enExample)
FR (1) FR2433830A1 (enExample)
GB (1) GB2025129B (enExample)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0413302U (enExample) * 1990-05-25 1992-02-03
JPH07214507A (ja) * 1994-06-13 1995-08-15 Noda Corp 建 材
JPH08207009A (ja) * 1995-11-17 1996-08-13 Tomiyasu Honda 積層板
JPH08207010A (ja) * 1995-11-17 1996-08-13 Tomiyasu Honda 積層板
JPH08309705A (ja) * 1996-03-11 1996-11-26 Noda Corp 建 材

Families Citing this family (61)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4295912A (en) * 1978-07-03 1981-10-20 National Semiconductor Corporation Apparatus and process for laminating composite tape
US4283839A (en) * 1978-07-26 1981-08-18 Western Electric Co., Inc. Method of bonding semiconductor devices to carrier tapes
US4439918A (en) * 1979-03-12 1984-04-03 Western Electric Co., Inc. Methods of packaging an electronic device
US4355463A (en) * 1980-03-24 1982-10-26 National Semiconductor Corporation Process for hermetically encapsulating semiconductor devices
EP0059187A1 (en) * 1980-09-08 1982-09-08 Mostek Corporation Single layer burn-in tape for integrated circuit
US4616412A (en) * 1981-01-13 1986-10-14 Schroeder Jon M Method for bonding electrical leads to electronic devices
US4438181A (en) 1981-01-13 1984-03-20 Jon M. Schroeder Electronic component bonding tape
FR2498814B1 (fr) * 1981-01-26 1985-12-20 Burroughs Corp Boitier pour circuit integre, moyen pour le montage et procede de fabrication
US4386389A (en) * 1981-09-08 1983-05-31 Mostek Corporation Single layer burn-in tape for integrated circuit
DE3378092D1 (en) * 1982-03-08 1988-10-27 Motorola Inc Integrated circuit lead frame
US4396457A (en) * 1982-03-17 1983-08-02 E. I. Du Pont De Nemours And Company Method of making bumped-beam tape
GB2172430B (en) * 1982-09-30 1987-05-07 Sumitomo Metal Mining Co Manufacture of carrier tapes
US4551912A (en) * 1983-06-30 1985-11-12 International Business Machines Corporation Highly integrated universal tape bonding
US4607779A (en) * 1983-08-11 1986-08-26 National Semiconductor Corporation Non-impact thermocompression gang bonding method
US4560826A (en) * 1983-12-29 1985-12-24 Amp Incorporated Hermetically sealed chip carrier
US4754912A (en) * 1984-04-05 1988-07-05 National Semiconductor Corporation Controlled collapse thermocompression gang bonding
DE3522852C2 (de) * 1985-06-26 1994-06-01 Gao Ges Automation Org Verfahren zur Herstellung eines Zwischenträgers für Halbleiterkörper
US4810620A (en) * 1985-06-26 1989-03-07 National Semiconductor Corporation Nickel plated tape
US4707418A (en) * 1985-06-26 1987-11-17 National Semiconductor Corporation Nickel plated copper tape
GB2178895B (en) * 1985-08-06 1988-11-23 Gen Electric Co Plc Improved preparation of fragile devices
US4701363A (en) * 1986-01-27 1987-10-20 Olin Corporation Process for manufacturing bumped tape for tape automated bonding and the product produced thereby
US4709468A (en) * 1986-01-31 1987-12-01 Texas Instruments Incorporated Method for producing an integrated circuit product having a polyimide film interconnection structure
GB2211351B (en) * 1986-02-28 1990-03-21 Seiko Epson Corp Method of forming an integrated circuit assembly or part thereof
US4795694A (en) * 1986-06-20 1989-01-03 Siemens Aktiengesellschaft Manufacture of fine structures for semiconductor contacting
DE3785720T2 (de) * 1986-09-25 1993-08-12 Toshiba Kawasaki Kk Verfahren zum herstellen eines filmtraegers.
US4735678A (en) * 1987-04-13 1988-04-05 Olin Corporation Forming a circuit pattern in a metallic tape by electrical discharge machining
US5106784A (en) * 1987-04-16 1992-04-21 Texas Instruments Incorporated Method of making a post molded cavity package with internal dam bar for integrated circuit
JPH0740600B2 (ja) * 1987-04-30 1995-05-01 三菱電機株式会社 半導体装置
JPH0526746Y2 (enExample) * 1987-07-14 1993-07-07
US4827376A (en) * 1987-10-05 1989-05-02 Olin Corporation Heat dissipating interconnect tape for use in tape automated bonding
US4849857A (en) * 1987-10-05 1989-07-18 Olin Corporation Heat dissipating interconnect tape for use in tape automated bonding
US5068712A (en) * 1988-09-20 1991-11-26 Hitachi, Ltd. Semiconductor device
JP2708191B2 (ja) * 1988-09-20 1998-02-04 株式会社日立製作所 半導体装置
US4967260A (en) * 1988-05-04 1990-10-30 International Electronic Research Corp. Hermetic microminiature packages
US4949161A (en) * 1988-12-23 1990-08-14 Micron Technology, Inc. Interdigitized leadframe strip
US5023202A (en) * 1989-07-14 1991-06-11 Lsi Logic Corporation Rigid strip carrier for integrated circuits
US5073521A (en) * 1989-11-15 1991-12-17 Olin Corporation Method for housing a tape-bonded electronic device and the package employed
DE4017863C1 (enExample) * 1990-06-02 1991-07-18 Du Pont De Nemours (Deutschland) Gmbh, 4000 Duesseldorf, De
USH1267H (en) 1990-07-05 1993-12-07 Boyd Melissa D Integrated circuit and lead frame assembly
US5060052A (en) * 1990-09-04 1991-10-22 Motorola, Inc. TAB bonded semiconductor device having off-chip power and ground distribution
KR930010072B1 (ko) * 1990-10-13 1993-10-14 금성일렉트론 주식회사 Ccd패키지 및 그 제조방법
FR2678428B1 (fr) * 1991-06-27 1993-09-03 Bull Sa Support et element de support de circuits integres et leur procede de fabrication.
US5545921A (en) * 1994-11-04 1996-08-13 International Business Machines, Corporation Personalized area leadframe coining or half etching for reduced mechanical stress at device edge
JP2626621B2 (ja) * 1995-04-21 1997-07-02 日本電気株式会社 半導体装置の製造方法
JP2894254B2 (ja) * 1995-09-20 1999-05-24 ソニー株式会社 半導体パッケージの製造方法
US6005287A (en) * 1995-11-24 1999-12-21 Nec Corporation Semiconductor device, and lead frame used therefor
JP3558459B2 (ja) * 1996-02-08 2004-08-25 沖電気工業株式会社 インナーリード接続方法
US6277225B1 (en) * 1996-03-13 2001-08-21 Micron Technology, Inc. Stress reduction feature for LOC lead frame
JPH09312374A (ja) * 1996-05-24 1997-12-02 Sony Corp 半導体パッケージ及びその製造方法
FR2749974B1 (fr) * 1996-06-13 1998-08-14 Bull Sa Procede de montage d'un circuit integre sur un support et support en resultant
KR100216064B1 (ko) * 1996-10-04 1999-08-16 윤종용 반도체 칩 패키지
JPH10150069A (ja) * 1996-11-21 1998-06-02 Sony Corp 半導体パッケージ及びその製造方法
US5923081A (en) 1997-05-15 1999-07-13 Micron Technology, Inc. Compression layer on the leadframe to reduce stress defects
US6222136B1 (en) 1997-11-12 2001-04-24 International Business Machines Corporation Printed circuit board with continuous connective bumps
JP2000173952A (ja) * 1998-12-03 2000-06-23 Fujitsu Quantum Device Kk 半導体装置及びその製造方法
US6782610B1 (en) * 1999-05-21 2004-08-31 North Corporation Method for fabricating a wiring substrate by electroplating a wiring film on a metal base
DE10014620A1 (de) * 2000-03-24 2001-09-27 Andreas Plettner Verfahren zur Herstellung eines Trägerbandes mit einer Vielzahl von elektrischen Einheiten, jeweils aufweisend einen Chip und Kontaktelemente
US7005729B2 (en) * 2002-04-24 2006-02-28 Intel Corporation Device packaging using tape automated bonding (TAB) strip bonded to strip carrier frame
US20040108580A1 (en) * 2002-12-09 2004-06-10 Advanpack Solutions Pte. Ltd. Leadless semiconductor packaging structure with inverted flip chip and methods of manufacture
JP2006278837A (ja) * 2005-03-30 2006-10-12 Mitsui Mining & Smelting Co Ltd フレキシブルプリント配線板の製造方法及びフレキシブルプリント配線板
KR102170192B1 (ko) 2013-08-22 2020-10-26 삼성전자주식회사 본딩 방법, 본딩 장치, 그리고 기판 제조 방법

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3440027A (en) * 1966-06-22 1969-04-22 Frances Hugle Automated packaging of semiconductors
US3480836A (en) * 1966-08-11 1969-11-25 Ibm Component mounted in a printed circuit
US3689991A (en) * 1968-03-01 1972-09-12 Gen Electric A method of manufacturing a semiconductor device utilizing a flexible carrier
US3763404A (en) * 1968-03-01 1973-10-02 Gen Electric Semiconductor devices and manufacture thereof
DE2151765C2 (de) * 1970-11-05 1983-06-16 Honeywell Information Systems Italia S.p.A., Caluso, Torino Verfahren zum Kontaktieren von integrierten Schaltungen mit Beam-Lead-Anschlüssen
US3781596A (en) * 1972-07-07 1973-12-25 R Galli Semiconductor chip carriers and strips thereof
US3838984A (en) * 1973-04-16 1974-10-01 Sperry Rand Corp Flexible carrier and interconnect for uncased ic chips
JPS501786A (enExample) * 1973-05-02 1975-01-09
DE2350026B2 (de) * 1973-10-05 1979-07-26 Robert Bosch Gmbh, 7000 Stuttgart Verfahren zur Herstellung einer mit einem isolierenden Träger verbundenen Vielfach-Elektrodenanordnung
US3968563A (en) * 1975-03-27 1976-07-13 E. I. Du Pont De Nemours And Company Precision registration system for leads
FR2311406A1 (fr) * 1975-05-13 1976-12-10 Honeywell Bull Soc Ind Perfectionnements aux procedes de fabrication de supports de conditionnement de micro-plaquettes de circuits integres
US4063993A (en) * 1975-07-07 1977-12-20 National Semiconductor Corporation Method of making gang bonding interconnect tape for semiconductive devices

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0413302U (enExample) * 1990-05-25 1992-02-03
JPH07214507A (ja) * 1994-06-13 1995-08-15 Noda Corp 建 材
JPH08207009A (ja) * 1995-11-17 1996-08-13 Tomiyasu Honda 積層板
JPH08207010A (ja) * 1995-11-17 1996-08-13 Tomiyasu Honda 積層板
JPH08309705A (ja) * 1996-03-11 1996-11-26 Noda Corp 建 材

Also Published As

Publication number Publication date
US4209355A (en) 1980-06-24
CA1124407A (en) 1982-05-25
JPS5519900A (en) 1980-02-12
DE2926200C2 (enExample) 1989-12-28
GB2025129B (en) 1982-12-01
GB2025129A (en) 1980-01-16
FR2433830B1 (enExample) 1983-11-10
FR2433830A1 (fr) 1980-03-14
DE2926200A1 (de) 1980-02-14

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