JPS6238748B2 - - Google Patents

Info

Publication number
JPS6238748B2
JPS6238748B2 JP55183477A JP18347780A JPS6238748B2 JP S6238748 B2 JPS6238748 B2 JP S6238748B2 JP 55183477 A JP55183477 A JP 55183477A JP 18347780 A JP18347780 A JP 18347780A JP S6238748 B2 JPS6238748 B2 JP S6238748B2
Authority
JP
Japan
Prior art keywords
data
command
input
length
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55183477A
Other languages
English (en)
Japanese (ja)
Other versions
JPS57106938A (en
Inventor
Junzo Tokimitsu
Seiichi Sugaya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18347780A priority Critical patent/JPS57106938A/ja
Publication of JPS57106938A publication Critical patent/JPS57106938A/ja
Publication of JPS6238748B2 publication Critical patent/JPS6238748B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
JP18347780A 1980-12-24 1980-12-24 Continuous processing system for undefined-length data Granted JPS57106938A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18347780A JPS57106938A (en) 1980-12-24 1980-12-24 Continuous processing system for undefined-length data

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18347780A JPS57106938A (en) 1980-12-24 1980-12-24 Continuous processing system for undefined-length data

Publications (2)

Publication Number Publication Date
JPS57106938A JPS57106938A (en) 1982-07-03
JPS6238748B2 true JPS6238748B2 (enrdf_load_stackoverflow) 1987-08-19

Family

ID=16136479

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18347780A Granted JPS57106938A (en) 1980-12-24 1980-12-24 Continuous processing system for undefined-length data

Country Status (1)

Country Link
JP (1) JPS57106938A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4853849A (en) * 1986-12-17 1989-08-01 Intel Corporation Multi-tasking register set mapping system which changes a register set pointer block bit during access instruction

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5852249B2 (ja) * 1978-12-25 1983-11-21 株式会社日立製作所 チヤネル装置

Also Published As

Publication number Publication date
JPS57106938A (en) 1982-07-03

Similar Documents

Publication Publication Date Title
JPS60160096A (ja) メモリ書き直し要求回路
JPS6238748B2 (enrdf_load_stackoverflow)
EP1014261A1 (en) Instruction look-ahead system and method
JPH0528431B2 (enrdf_load_stackoverflow)
JP2758624B2 (ja) マイクロプログラムの調速方式
JPS62279438A (ja) トレ−ス回路
KR100246465B1 (ko) 마이크로프로세서 스택 명령어의 수행사이클을 줄이기 위한 장치 및 그 방법
JPS595932B2 (ja) デ−タ処理方式
JP3124361B2 (ja) メモリデータロード装置
JPS59188900A (ja) デ−タ処理装置
JP2845780B2 (ja) データ転送制御回路
JP2764947B2 (ja) 命令制御方式
JPS63120336A (ja) メモリアクセスモ−ド切替え方式
JPH0234058B2 (enrdf_load_stackoverflow)
JPS6149695B2 (enrdf_load_stackoverflow)
JPH0553759A (ja) 固定小数点演算ユニツト
JPH0580691B2 (enrdf_load_stackoverflow)
JPH02122302A (ja) シーケンス処理回路
JPS59105110A (ja) プログラマブルコントロ−ラ
JPH02242349A (ja) コマンド処理装置
JPS599936B2 (ja) デ−タ監視装置
JPS6115235A (ja) 中央処理装置
JPH10320380A (ja) ベクトル処理装置
JPS58155587A (ja) 処理装置
JPS625448A (ja) 情報履歴記憶方式