JPS57106938A - Continuous processing system for undefined-length data - Google Patents

Continuous processing system for undefined-length data

Info

Publication number
JPS57106938A
JPS57106938A JP18347780A JP18347780A JPS57106938A JP S57106938 A JPS57106938 A JP S57106938A JP 18347780 A JP18347780 A JP 18347780A JP 18347780 A JP18347780 A JP 18347780A JP S57106938 A JPS57106938 A JP S57106938A
Authority
JP
Japan
Prior art keywords
data
length
register
counter
command
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18347780A
Other languages
Japanese (ja)
Other versions
JPS6238748B2 (en
Inventor
Jiyunzou Tokimitsu
Seiichi Sugaya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18347780A priority Critical patent/JPS57106938A/en
Publication of JPS57106938A publication Critical patent/JPS57106938A/en
Publication of JPS6238748B2 publication Critical patent/JPS6238748B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To process undefined-length data continuously at a high speed with high efficiency, by reporting the length of data processed actually through the specification of a specific flag on an input and output command. CONSTITUTION:An input and output command consists of a command code 1, a data address part 2, a processed-data-length reporting flag 3, and a data-length specification part 4. In an address register 10, an address for access to a main storage device MS is held, and the address part 2 is set as an initial value and updated each time data transfer is performed; and data length is calculated by an adding circuit 11 after a command is executed, and then set in the register 10 through a register 12. Transfer data length is controlled by a counter 13 and decreased each time data is transferred to or from the MS and when the counter value goes down to zero, the data transfer is stopped. Processed data length is counted by a counter 14 and data from an I/O is set in a data register 15 and transferred to the MS; the value of the counter 14 is set after a command is executed and transferred to the MS.
JP18347780A 1980-12-24 1980-12-24 Continuous processing system for undefined-length data Granted JPS57106938A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18347780A JPS57106938A (en) 1980-12-24 1980-12-24 Continuous processing system for undefined-length data

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18347780A JPS57106938A (en) 1980-12-24 1980-12-24 Continuous processing system for undefined-length data

Publications (2)

Publication Number Publication Date
JPS57106938A true JPS57106938A (en) 1982-07-03
JPS6238748B2 JPS6238748B2 (en) 1987-08-19

Family

ID=16136479

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18347780A Granted JPS57106938A (en) 1980-12-24 1980-12-24 Continuous processing system for undefined-length data

Country Status (1)

Country Link
JP (1) JPS57106938A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63238631A (en) * 1986-12-17 1988-10-04 インテル・コーポレーション Execution apparatus for i/o processor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5587221A (en) * 1978-12-25 1980-07-01 Hitachi Ltd Channel unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5587221A (en) * 1978-12-25 1980-07-01 Hitachi Ltd Channel unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63238631A (en) * 1986-12-17 1988-10-04 インテル・コーポレーション Execution apparatus for i/o processor

Also Published As

Publication number Publication date
JPS6238748B2 (en) 1987-08-19

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