JPS62169358A - 半導体集積回路装置の製法 - Google Patents

半導体集積回路装置の製法

Info

Publication number
JPS62169358A
JPS62169358A JP61309744A JP30974486A JPS62169358A JP S62169358 A JPS62169358 A JP S62169358A JP 61309744 A JP61309744 A JP 61309744A JP 30974486 A JP30974486 A JP 30974486A JP S62169358 A JPS62169358 A JP S62169358A
Authority
JP
Japan
Prior art keywords
type
transistor
vertical
base
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61309744A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6255307B2 (enExample
Inventor
Yoshio Ueki
植木　善夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP61309744A priority Critical patent/JPS62169358A/ja
Publication of JPS62169358A publication Critical patent/JPS62169358A/ja
Publication of JPS6255307B2 publication Critical patent/JPS6255307B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/65—Integrated injection logic
    • H10D84/658—Integrated injection logic integrated in combination with analog structures

Landscapes

  • Bipolar Integrated Circuits (AREA)
JP61309744A 1986-12-27 1986-12-27 半導体集積回路装置の製法 Granted JPS62169358A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61309744A JPS62169358A (ja) 1986-12-27 1986-12-27 半導体集積回路装置の製法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61309744A JPS62169358A (ja) 1986-12-27 1986-12-27 半導体集積回路装置の製法

Publications (2)

Publication Number Publication Date
JPS62169358A true JPS62169358A (ja) 1987-07-25
JPS6255307B2 JPS6255307B2 (enExample) 1987-11-19

Family

ID=17996773

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61309744A Granted JPS62169358A (ja) 1986-12-27 1986-12-27 半導体集積回路装置の製法

Country Status (1)

Country Link
JP (1) JPS62169358A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008039965A (ja) * 2006-08-03 2008-02-21 Konica Minolta Business Technologies Inc 現像装置及び画像形成装置
US7406280B2 (en) 2003-09-09 2008-07-29 Sharp Kabushiki Kaisha Magnet roller developing device and image forming apparatus for reducing obstructions in developer circulation path

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7406280B2 (en) 2003-09-09 2008-07-29 Sharp Kabushiki Kaisha Magnet roller developing device and image forming apparatus for reducing obstructions in developer circulation path
JP2008039965A (ja) * 2006-08-03 2008-02-21 Konica Minolta Business Technologies Inc 現像装置及び画像形成装置

Also Published As

Publication number Publication date
JPS6255307B2 (enExample) 1987-11-19

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