JPS6196578U

JPS6196578U -

Info

Publication number: JPS6196578U
Application number: JP18176184U
Authority: JP
Priority date: 1984-11-30
Filing date: 1984-11-30
Publication date: 1986-06-21

Description

[Brief explanation of the drawing]

第１図イ，ロ，ハは本考案の一実施例を説明す
る断面図、第２図イ，ロは本考案の別の実施例を
説明する断面図、第３図イ，ロは本考案のプリン
ト板のパターン走行を示し、イは断面図、ロは各
層パターン走行を示す斜視図、第４図、第５図、
第６図は従来の多層プリント板の層間接続を説明
する断面図、第７図は従来のスルーホール穴を避
けた配線パターンを説明する図である。図において、１は銅箔、２は絶縁層、５，８は
メツキ、７，９は穴を示す。 Figure 1 A, B and C are sectional views explaining one embodiment of the present invention, Figure 2 A and B are sectional views explaining another embodiment of the present invention, and Figure 3 A and B are sectional views explaining the present invention. 4 shows the pattern running of the printed board, A is a cross-sectional view, B is a perspective view showing the pattern running of each layer, FIGS. 4 and 5,
FIG. 6 is a sectional view illustrating interlayer connections of a conventional multilayer printed board, and FIG. 7 is a diagram illustrating a wiring pattern that avoids conventional through-holes. In the figure, 1 is a copper foil, 2 is an insulating layer, 5 and 8 are platings, and 7 and 9 are holes.

Claims

[Scope of utility model registration request]

For each layer printed board, a hole is made in the insulating layer between the surface layer pattern and the second layer pattern, or between the back layer pattern and the layer pattern one layer before the back layer pattern, and the holes are removed. A well-type through-hole printed board characterized in that electrolytic plating and electrolytic plating are performed to connect the surface layer pattern and the second layer pattern, or the back layer pattern and the layer pattern one layer before the back layer.