JPS6148037A - 浮動小数点演算装置 - Google Patents

浮動小数点演算装置

Info

Publication number
JPS6148037A
JPS6148037A JP60101691A JP10169185A JPS6148037A JP S6148037 A JPS6148037 A JP S6148037A JP 60101691 A JP60101691 A JP 60101691A JP 10169185 A JP10169185 A JP 10169185A JP S6148037 A JPS6148037 A JP S6148037A
Authority
JP
Japan
Prior art keywords
register
bus
input
result
multiplication
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60101691A
Other languages
English (en)
Japanese (ja)
Other versions
JPH03653B2 (Direct
Inventor
リチヤード・ダグラス・デグルート
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS6148037A publication Critical patent/JPS6148037A/ja
Publication of JPH03653B2 publication Critical patent/JPH03653B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30141—Implementation provisions of register files, e.g. ports
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/3884—Pipelining

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Advance Control (AREA)
  • Complex Calculations (AREA)
JP60101691A 1984-08-13 1985-05-15 浮動小数点演算装置 Granted JPS6148037A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/639,754 US4766564A (en) 1984-08-13 1984-08-13 Dual putaway/bypass busses for multiple arithmetic units
US639754 1984-08-13

Publications (2)

Publication Number Publication Date
JPS6148037A true JPS6148037A (ja) 1986-03-08
JPH03653B2 JPH03653B2 (Direct) 1991-01-08

Family

ID=24565411

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60101691A Granted JPS6148037A (ja) 1984-08-13 1985-05-15 浮動小数点演算装置

Country Status (4)

Country Link
US (1) US4766564A (Direct)
EP (1) EP0171595B1 (Direct)
JP (1) JPS6148037A (Direct)
DE (1) DE3582533D1 (Direct)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5980598A (ja) * 1982-10-27 1984-05-10 日邦バルブ工業株式会社 サドル型分水栓
JPS6186840A (ja) * 1984-09-27 1986-05-02 アドバンスト・マイクロ・デイバイシズ・インコーポレーテツド 完全組合わせ算術装置
JPH0194477A (ja) * 1987-10-06 1989-04-13 Nec Corp シグナルプロセッサ
JPH01133138A (ja) * 1987-11-19 1989-05-25 Hitachi Ltd 並列計算機及びその制御方法
JPH01255031A (ja) * 1988-04-05 1989-10-11 Matsushita Electric Ind Co Ltd 演算処理装置
JPH01266669A (ja) * 1988-04-19 1989-10-24 Mitsubishi Electric Corp 数値計算装置
JPH025179A (ja) * 1988-01-29 1990-01-10 Texas Instr Inc <Ti> データを処理する集積回路
JPH02103624A (ja) * 1988-10-12 1990-04-16 Hitachi Ltd データ処理装置
JPH06282418A (ja) * 1993-03-30 1994-10-07 N T T Idou Tsuushinmou Kk 演算装置
JPH07114455A (ja) * 1993-09-29 1995-05-02 Internatl Business Mach Corp <Ibm> パイプライン浮動小数点プロセッサ及びその乗算・加算命令シーケンスの実行

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4683547A (en) * 1984-10-25 1987-07-28 International Business Machines Corporation Special accumulate instruction for multiple floating point arithmetic units which use a putaway bus to enhance performance
US4766566A (en) * 1986-08-18 1988-08-23 International Business Machines Corp. Performance enhancement scheme for a RISC type VLSI processor using dual execution units for parallel instruction processing
JP2810068B2 (ja) * 1988-11-11 1998-10-15 株式会社日立製作所 プロセッサシステム、コンピュータシステム及び命令処理方法
US4999802A (en) * 1989-01-13 1991-03-12 International Business Machines Corporation Floating point arithmetic two cycle data flow
US5212662A (en) * 1989-01-13 1993-05-18 International Business Machines Corporation Floating point arithmetic two cycle data flow
CA2007059C (en) * 1989-01-27 1994-05-24 Steven P. Davies Register and arithmetic logic unit
US5204828A (en) * 1989-02-10 1993-04-20 Intel Corporation Bus apparatus having hold registers for parallel processing in a microprocessor
US5175863A (en) * 1989-10-23 1992-12-29 International Business Machines Corporation Signal data processing system having independently, simultaneously operable alu and macu
US5053987A (en) * 1989-11-02 1991-10-01 Zoran Corporation Arithmetic unit in a vector signal processor using pipelined computational blocks
US5058048A (en) * 1990-04-02 1991-10-15 Advanced Micro Devices, Inc. Normalizing pipelined floating point processing unit
US5053631A (en) * 1990-04-02 1991-10-01 Advanced Micro Devices, Inc. Pipelined floating point processing unit
US5128888A (en) * 1990-04-02 1992-07-07 Advanced Micro Devices, Inc. Arithmetic unit having multiple accumulators
US5268854A (en) * 1990-11-13 1993-12-07 Kabushiki Kaisha Toshiba Microprocessor with a function for three-dimensional graphic processing
DE69228083T2 (de) * 1991-03-14 1999-05-20 Fujitsu Ltd., Kawasaki, Kanagawa Verfahren und Vorrichtung zur Steuerung von Pipelineoperationen
US5961629A (en) * 1991-07-08 1999-10-05 Seiko Epson Corporation High performance, superscalar-based computer system with out-of-order instruction execution
EP0945787A3 (en) * 1991-07-08 2008-12-31 Seiko Epson Corporation Risc microprocessor architecture implementing fast trap and exception state
US5539911A (en) * 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
WO1993001546A1 (en) 1991-07-08 1993-01-21 Seiko Epson Corporation Extensible risc microprocessor architecture
JPH0614003A (ja) * 1991-07-31 1994-01-21 Nec Corp データ処理回路
US5438668A (en) 1992-03-31 1995-08-01 Seiko Epson Corporation System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer
US6735685B1 (en) 1992-09-29 2004-05-11 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
EP0663083B1 (en) 1992-09-29 2000-12-20 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US6092184A (en) * 1995-12-28 2000-07-18 Intel Corporation Parallel processing of pipelined instructions having register dependencies
US6041387A (en) * 1997-09-12 2000-03-21 Siemens Aktiengesellschaft Apparatus for read/write-access to registers having register file architecture in a central processing unit
US6301653B1 (en) * 1998-10-14 2001-10-09 Conexant Systems, Inc. Processor containing data path units with forwarding paths between two data path units and a unique configuration or register blocks
US6606700B1 (en) * 2000-02-26 2003-08-12 Qualcomm, Incorporated DSP with dual-mac processor and dual-mac coprocessor
US7269719B2 (en) * 2002-10-30 2007-09-11 Stmicroelectronics, Inc. Predicated execution using operand predicates
CN101916182B (zh) * 2009-09-09 2014-08-20 威盛电子股份有限公司 使用非架构的数据格式的快速浮点结果的转送
US11269651B2 (en) * 2019-09-10 2022-03-08 International Business Machines Corporation Reusing adjacent SIMD unit for fast wide result generation

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3697734A (en) * 1970-07-28 1972-10-10 Singer Co Digital computer utilizing a plurality of parallel asynchronous arithmetic units
US4179734A (en) * 1976-07-02 1979-12-18 Floating Point Systems, Inc. Floating point data processor having fast access memory means
US4075704A (en) * 1976-07-02 1978-02-21 Floating Point Systems, Inc. Floating point data processor for high speech operation
US4205373A (en) * 1978-05-22 1980-05-27 Ncr Corporation System and method for accessing memory connected to different bus and requesting subsystem
DE3066955D1 (en) * 1980-06-24 1984-04-19 Ibm Signal processor computing arrangement and method of operating said arrangement
JPS57155666A (en) * 1981-03-20 1982-09-25 Fujitsu Ltd Instruction controlling system of vector processor
JPS592143A (ja) * 1982-06-29 1984-01-07 Hitachi Ltd 情報処理装置
JPS5932045A (ja) * 1982-08-16 1984-02-21 Hitachi Ltd 情報処理装置
US4553203A (en) * 1982-09-28 1985-11-12 Trw Inc. Easily schedulable horizontal computer
US4594660A (en) * 1982-10-13 1986-06-10 Honeywell Information Systems Inc. Collector
US4594655A (en) * 1983-03-14 1986-06-10 International Business Machines Corporation (k)-Instructions-at-a-time pipelined processor for parallel execution of inherently sequential instructions
US4630195A (en) * 1984-05-31 1986-12-16 International Business Machines Corporation Data processing system with CPU register to register data transfers overlapped with data transfer to and from main storage

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5980598A (ja) * 1982-10-27 1984-05-10 日邦バルブ工業株式会社 サドル型分水栓
JPS6186840A (ja) * 1984-09-27 1986-05-02 アドバンスト・マイクロ・デイバイシズ・インコーポレーテツド 完全組合わせ算術装置
JPH0194477A (ja) * 1987-10-06 1989-04-13 Nec Corp シグナルプロセッサ
JPH01133138A (ja) * 1987-11-19 1989-05-25 Hitachi Ltd 並列計算機及びその制御方法
JPH025179A (ja) * 1988-01-29 1990-01-10 Texas Instr Inc <Ti> データを処理する集積回路
JPH01255031A (ja) * 1988-04-05 1989-10-11 Matsushita Electric Ind Co Ltd 演算処理装置
JPH01266669A (ja) * 1988-04-19 1989-10-24 Mitsubishi Electric Corp 数値計算装置
JPH02103624A (ja) * 1988-10-12 1990-04-16 Hitachi Ltd データ処理装置
JPH06282418A (ja) * 1993-03-30 1994-10-07 N T T Idou Tsuushinmou Kk 演算装置
JPH07114455A (ja) * 1993-09-29 1995-05-02 Internatl Business Mach Corp <Ibm> パイプライン浮動小数点プロセッサ及びその乗算・加算命令シーケンスの実行

Also Published As

Publication number Publication date
EP0171595A3 (en) 1988-01-13
JPH03653B2 (Direct) 1991-01-08
EP0171595B1 (en) 1991-04-17
DE3582533D1 (de) 1991-05-23
EP0171595A2 (en) 1986-02-19
US4766564A (en) 1988-08-23

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