JPS613599U - 半導体メモリイ装置 - Google Patents

半導体メモリイ装置

Info

Publication number
JPS613599U
JPS613599U JP1985071582U JP7158285U JPS613599U JP S613599 U JPS613599 U JP S613599U JP 1985071582 U JP1985071582 U JP 1985071582U JP 7158285 U JP7158285 U JP 7158285U JP S613599 U JPS613599 U JP S613599U
Authority
JP
Japan
Prior art keywords
field effect
effect transistor
variable threshold
circuit
threshold field
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1985071582U
Other languages
English (en)
Other versions
JPS6280Y2 (ja
Inventor
ジエイムズ・ロナルド・クリツチ
Original Assignee
ウエスチングハウス エレクトリック コ−ポレ−ション
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ウエスチングハウス エレクトリック コ−ポレ−ション filed Critical ウエスチングハウス エレクトリック コ−ポレ−ション
Publication of JPS613599U publication Critical patent/JPS613599U/ja
Application granted granted Critical
Publication of JPS6280Y2 publication Critical patent/JPS6280Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/01855—Interface arrangements synchronous, i.e. using clock signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Read Only Memory (AREA)
  • Dram (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】

Claims (1)

  1. 【実用新案登録請求の範囲】 “一 −− １ 第１可変閾値電界効果トランジスタおよび第２−可
    変閾値電界効果トランジスタを有する少なくとも１個の
    メモリイ・モルと、上記第１旬変，閾値電界効果トラン
    ジス−タの閾値電圧を変えるための第１回路装置であっ
    て上記閾値電圧を上昇させるための回路を含むものと、
    上記第１回路装置に付随して上記第２可変閾値電界効果
    トラジジスタの閾値電圧を変えるための第２回路装置で
    あって上記閾値電圧を降乍させるための回路を含むもの
    とを備えた情報記憶用半導体メモリイ装置であって、更
    に、両方のトランジスタへ互に反対の方向で書込むため
    の手段と、新しい書込み情報を上記メモリイ・セルに既
    に存在する記憶情報と比較するためのかつ両方の情報が
    異なる時だけ上記新しい書込み情報を書込ませるための
    比較手段とを含９半導体メモリイ装置。 ２ 第１回路装置は、第１可弯閾値電界効果トラ′ンジ
    スタのゲートへ接続された第１行デコーダおよび上記第
    １可変閾値電界効果トランジスタのソースと基板へ接続
    された第１列レコーダ回路装置を含む実用新案登録請求
    の範囲第１項記載の半導体メモリイ装置。 ３ 第２回路装置は、第２可変閾値電界効果トラ、ンジ
    スタのゲートへ接続された第２列デコーダおよび上記第
    ２可変閾値電界一果トランジスタ． めソースと基板へ
    接続された第２列レコーダ回 ，路装置を含む★用新案
    登録請求の範囲第１項または第２項記載の半導体メモリ
    イ装置。 ４ 少なくとも第１可変閾値電界効果トランジスタは、
    窒化シリコンの層および二酸化シリコン層のから成るゲ
    ート絶縁体を有する実用新率登録請求の範囲第１項ない
    し第３項のいずれかに
JP1985071582U 1976-12-29 1985-05-16 半導体メモリイ装置 Granted JPS613599U (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/755,280 US4090258A (en) 1976-12-29 1976-12-29 MNOS non-volatile memory with write cycle suppression
US755280 1976-12-29

Publications (2)

Publication Number Publication Date
JPS613599U true JPS613599U (ja) 1986-01-10
JPS6280Y2 JPS6280Y2 (ja) 1987-01-06

Family

ID=25038492

Family Applications (2)

Application Number Title Priority Date Filing Date
JP15661277A Pending JPS5384433A (en) 1976-12-29 1977-12-27 Semiconductor memory
JP1985071582U Granted JPS613599U (ja) 1976-12-29 1985-05-16 半導体メモリイ装置

Family Applications Before (1)

Application Number Title Priority Date Filing Date
JP15661277A Pending JPS5384433A (en) 1976-12-29 1977-12-27 Semiconductor memory

Country Status (4)

Country Link
US (1) US4090258A (ja)
JP (2) JPS5384433A (ja)
DE (1) DE2757987A1 (ja)
FR (1) FR2376495A1 (ja)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4611308A (en) * 1978-06-29 1986-09-09 Westinghouse Electric Corp. Drain triggered N-channel non-volatile memory
US4179626A (en) * 1978-06-29 1979-12-18 Westinghouse Electric Corp. Sense circuit for use in variable threshold transistor memory arrays
JPS5671884A (en) * 1979-11-15 1981-06-15 Nippon Texas Instr Kk Nonvolatile semiconductor storage device
JPS5693363A (en) * 1979-12-04 1981-07-28 Fujitsu Ltd Semiconductor memory
US4398269A (en) * 1981-07-23 1983-08-09 Sperry Corporation MNOS Over-write protection circuitry
EP0082208B1 (de) * 1981-12-17 1985-11-21 Deutsche ITT Industries GmbH Integrierter CMOS-Schaltkreis
US4575823A (en) * 1982-08-17 1986-03-11 Westinghouse Electric Corp. Electrically alterable non-volatile memory
US4535428A (en) * 1983-03-10 1985-08-13 International Business Machines Corporation Multi-port register implementations
US4616347A (en) * 1983-05-31 1986-10-07 International Business Machines Corporation Multi-port system
US4558433A (en) * 1983-05-31 1985-12-10 International Business Machines Corporation Multi-port register implementations
US4577292A (en) * 1983-05-31 1986-03-18 International Business Machines Corporation Support circuitry for multi-port systems
US4578777A (en) * 1983-07-11 1986-03-25 Signetics Corporation One step write circuit arrangement for EEPROMS
US4566080A (en) * 1983-07-11 1986-01-21 Signetics Corporation Byte wide EEPROM with individual write circuits
US4599707A (en) * 1984-03-01 1986-07-08 Signetics Corporation Byte wide EEPROM with individual write circuits and write prevention means
JPS62165793A (ja) * 1986-01-17 1987-07-22 Toshiba Corp 連想メモリ
FR2620246B1 (fr) * 1987-03-31 1989-11-24 Smh Alcatel Memoire non volatile a faible taux d'ecriture et machine a affranchir en faisant application
US4811296A (en) * 1987-05-15 1989-03-07 Analog Devices, Inc. Multi-port register file with flow-through of data
US5268319A (en) 1988-06-08 1993-12-07 Eliyahou Harari Highly compact EPROM and flash EEPROM devices
JPH02260298A (ja) * 1989-03-31 1990-10-23 Oki Electric Ind Co Ltd 不揮発性多値メモリ装置
US7447069B1 (en) 1989-04-13 2008-11-04 Sandisk Corporation Flash EEprom system
DE69034227T2 (de) 1989-04-13 2007-05-03 Sandisk Corp., Sunnyvale EEprom-System mit Blocklöschung
US5218569A (en) 1991-02-08 1993-06-08 Banks Gerald J Electrically alterable non-volatile memory with n-bits per memory cell
US6002614A (en) 1991-02-08 1999-12-14 Btg International Inc. Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell
JP2502008B2 (ja) * 1992-06-04 1996-05-29 株式会社東芝 不揮発性半導体メモリ
US6353554B1 (en) 1995-02-27 2002-03-05 Btg International Inc. Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell
JP3863124B2 (ja) * 2003-05-08 2006-12-27 株式会社東芝 半導体記憶装置及びそのテスト方法
US6870772B1 (en) * 2003-09-12 2005-03-22 Renesas Technology Corp. Nonvolatile semiconductor memory device
US7283390B2 (en) * 2004-04-21 2007-10-16 Impinj, Inc. Hybrid non-volatile memory
US8111558B2 (en) * 2004-05-05 2012-02-07 Synopsys, Inc. pFET nonvolatile memory
US7894261B1 (en) 2008-05-22 2011-02-22 Synopsys, Inc. PFET nonvolatile memory

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3579204A (en) * 1969-03-24 1971-05-18 Sperry Rand Corp Variable conduction threshold transistor memory circuit insensitive to threshold deviations
JPS50131723A (ja) * 1974-04-04 1975-10-18

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2135625B1 (de) * 1971-07-16 1973-01-04 Ibm Deutschland Gmbh, 7000 Stuttgart Schaltungsanordnung zur automatischen Schreib-Unterdrückung
DE2347968C3 (de) * 1973-09-24 1980-06-26 Siemens Ag, 1000 Berlin Und 8000 Muenchen Assoziative Speicherzelle
US3836894A (en) * 1974-01-22 1974-09-17 Westinghouse Electric Corp Mnos/sos random access memory

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3579204A (en) * 1969-03-24 1971-05-18 Sperry Rand Corp Variable conduction threshold transistor memory circuit insensitive to threshold deviations
JPS50131723A (ja) * 1974-04-04 1975-10-18

Also Published As

Publication number Publication date
FR2376495A1 (fr) 1978-07-28
DE2757987A1 (de) 1978-07-06
JPS6280Y2 (ja) 1987-01-06
US4090258A (en) 1978-05-16
JPS5384433A (en) 1978-07-25

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