JPS6130300B2 - - Google Patents

Info

Publication number
JPS6130300B2
JPS6130300B2 JP56107472A JP10747281A JPS6130300B2 JP S6130300 B2 JPS6130300 B2 JP S6130300B2 JP 56107472 A JP56107472 A JP 56107472A JP 10747281 A JP10747281 A JP 10747281A JP S6130300 B2 JPS6130300 B2 JP S6130300B2
Authority
JP
Japan
Prior art keywords
module
memory
cpu
input
main memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56107472A
Other languages
English (en)
Japanese (ja)
Other versions
JPS588366A (ja
Inventor
Toshikatsu Watabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP56107472A priority Critical patent/JPS588366A/ja
Publication of JPS588366A publication Critical patent/JPS588366A/ja
Publication of JPS6130300B2 publication Critical patent/JPS6130300B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0692—Multiconfiguration, e.g. local and global addressing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)
  • Memory System (AREA)
JP56107472A 1981-07-09 1981-07-09 メモリモジユ−ルシステム Granted JPS588366A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56107472A JPS588366A (ja) 1981-07-09 1981-07-09 メモリモジユ−ルシステム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56107472A JPS588366A (ja) 1981-07-09 1981-07-09 メモリモジユ−ルシステム

Publications (2)

Publication Number Publication Date
JPS588366A JPS588366A (ja) 1983-01-18
JPS6130300B2 true JPS6130300B2 (enrdf_load_html_response) 1986-07-12

Family

ID=14460060

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56107472A Granted JPS588366A (ja) 1981-07-09 1981-07-09 メモリモジユ−ルシステム

Country Status (1)

Country Link
JP (1) JPS588366A (enrdf_load_html_response)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63104084A (ja) * 1986-10-22 1988-05-09 株式会社日立製作所 Ｃｒｔコントロ−ラ
JPS63106897A (ja) * 1986-10-24 1988-05-11 能美防災株式会社 防災装置などに使用される多ポ−トｒａｍ
JPS63284648A (ja) * 1987-05-18 1988-11-21 Fujitsu Ltd キャッシュメモリ制御方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
b¨m®MULTIVUSýÐc±lxbýÐ=S55 *

Also Published As

Publication number Publication date
JPS588366A (ja) 1983-01-18

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