JPS6127681A - 超格子構造のチヤネル部をもつ電界効果トランジスタ - Google Patents

超格子構造のチヤネル部をもつ電界効果トランジスタ

Info

Publication number
JPS6127681A
JPS6127681A JP14795784A JP14795784A JPS6127681A JP S6127681 A JPS6127681 A JP S6127681A JP 14795784 A JP14795784 A JP 14795784A JP 14795784 A JP14795784 A JP 14795784A JP S6127681 A JPS6127681 A JP S6127681A
Authority
JP
Japan
Prior art keywords
superlattice structure
field effect
effect transistor
layer
channel part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14795784A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0224025B2 (enrdf_load_stackoverflow
Inventor
Zenko Hirose
全孝 廣瀬
Seiichi Miyazaki
誠一 宮崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Science and Technology Agency
Original Assignee
Research Development Corp of Japan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Research Development Corp of Japan filed Critical Research Development Corp of Japan
Priority to JP14795784A priority Critical patent/JPS6127681A/ja
Publication of JPS6127681A publication Critical patent/JPS6127681A/ja
Publication of JPH0224025B2 publication Critical patent/JPH0224025B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6748—Group IV materials, e.g. germanium or silicon carbide having a multilayer structure or superlattice structure

Landscapes

  • Junction Field-Effect Transistors (AREA)
  • Recrystallisation Techniques (AREA)
JP14795784A 1984-07-17 1984-07-17 超格子構造のチヤネル部をもつ電界効果トランジスタ Granted JPS6127681A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14795784A JPS6127681A (ja) 1984-07-17 1984-07-17 超格子構造のチヤネル部をもつ電界効果トランジスタ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14795784A JPS6127681A (ja) 1984-07-17 1984-07-17 超格子構造のチヤネル部をもつ電界効果トランジスタ

Publications (2)

Publication Number Publication Date
JPS6127681A true JPS6127681A (ja) 1986-02-07
JPH0224025B2 JPH0224025B2 (enrdf_load_stackoverflow) 1990-05-28

Family

ID=15441903

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14795784A Granted JPS6127681A (ja) 1984-07-17 1984-07-17 超格子構造のチヤネル部をもつ電界効果トランジスタ

Country Status (1)

Country Link
JP (1) JPS6127681A (enrdf_load_stackoverflow)

Cited By (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61230374A (ja) * 1985-04-05 1986-10-14 Seiko Epson Corp 電界効果型トランジスタ及びその製造方法
JPS62279672A (ja) * 1986-05-28 1987-12-04 Kanegafuchi Chem Ind Co Ltd 半導体装置
JPS6394680A (ja) * 1986-10-08 1988-04-25 Semiconductor Energy Lab Co Ltd 絶縁ゲイト型電界効果半導体装置
JPS6394681A (ja) * 1986-10-08 1988-04-25 Semiconductor Energy Lab Co Ltd 絶縁ゲイト型電界効果半導体装置の作製方法
JPS6394682A (ja) * 1986-10-08 1988-04-25 Semiconductor Energy Lab Co Ltd 絶縁ゲイト型電界効果半導体装置
US4806998A (en) * 1986-06-30 1989-02-21 Thomson-Csf Heterojunction and dual channel semiconductor field effect transistor or negative transconductive device
US4908678A (en) * 1986-10-08 1990-03-13 Semiconductor Energy Laboratory Co., Ltd. FET with a super lattice channel
US5051786A (en) * 1989-10-24 1991-09-24 Mcnc Passivated polycrystalline semiconductors quantum well/superlattice structures fabricated thereof
EP0694756A2 (en) 1994-07-27 1996-01-31 Shimadzu Corporation Elongation measurement using a laser non-contact extensometer
WO2002001641A1 (en) * 2000-06-27 2002-01-03 Matsushita Electric Industrial Co., Ltd. Semiconductor device
WO2002043157A1 (en) * 2000-11-21 2002-05-30 Matsushita Electric Industrial Co.,Ltd. Semiconductor device and its manufacturing method
US6460418B1 (en) 2000-01-19 2002-10-08 Kishimoto Sangyo Co., Ltd. Method of and apparatus for measuring elongation of a test specimen
WO2005018005A1 (en) * 2003-06-26 2005-02-24 Rj Mears, Llc Semiconductor device including mosfet having band-engineered superlattice
WO2005018004A1 (en) * 2003-06-26 2005-02-24 Rj Mears, Llc Method for making semiconductor device including band-engineered superlattice
WO2005034245A1 (en) * 2003-06-26 2005-04-14 Rj Mears, Llc Semiconductor device including band-engineered superlattice
US6993222B2 (en) 1999-03-03 2006-01-31 Rj Mears, Llc Optical filter device with aperiodically arranged grating elements
US7045813B2 (en) 2003-06-26 2006-05-16 Rj Mears, Llc Semiconductor device including a superlattice with regions defining a semiconductor junction
US7045377B2 (en) 2003-06-26 2006-05-16 Rj Mears, Llc Method for making a semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
US7123792B1 (en) 1999-03-05 2006-10-17 Rj Mears, Llc Configurable aperiodic grating device
US7227174B2 (en) 2003-06-26 2007-06-05 Rj Mears, Llc Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
US7229902B2 (en) 2003-06-26 2007-06-12 Rj Mears, Llc Method for making a semiconductor device including a superlattice with regions defining a semiconductor junction
US7446002B2 (en) 2003-06-26 2008-11-04 Mears Technologies, Inc. Method for making a semiconductor device comprising a superlattice dielectric interface layer
US7491587B2 (en) 2003-06-26 2009-02-17 Mears Technologies, Inc. Method for making a semiconductor device having a semiconductor-on-insulator (SOI) configuration and including a superlattice on a thin semiconductor layer
US7514328B2 (en) 2003-06-26 2009-04-07 Mears Technologies, Inc. Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween
US7517702B2 (en) 2005-12-22 2009-04-14 Mears Technologies, Inc. Method for making an electronic device including a poled superlattice having a net electrical dipole moment
US7531828B2 (en) 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions
US7531850B2 (en) 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including a memory cell with a negative differential resistance (NDR) device
US7531829B2 (en) 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance
US7535041B2 (en) 2003-06-26 2009-05-19 Mears Technologies, Inc. Method for making a semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance
US7586165B2 (en) 2003-06-26 2009-09-08 Mears Technologies, Inc. Microelectromechanical systems (MEMS) device including a superlattice
US7586116B2 (en) 2003-06-26 2009-09-08 Mears Technologies, Inc. Semiconductor device having a semiconductor-on-insulator configuration and a superlattice
US7598515B2 (en) 2003-06-26 2009-10-06 Mears Technologies, Inc. Semiconductor device including a strained superlattice and overlying stress layer and related methods
US7612366B2 (en) 2003-06-26 2009-11-03 Mears Technologies, Inc. Semiconductor device including a strained superlattice layer above a stress layer
US7659539B2 (en) 2003-06-26 2010-02-09 Mears Technologies, Inc. Semiconductor device including a floating gate memory cell with a superlattice channel
US7700447B2 (en) 2006-02-21 2010-04-20 Mears Technologies, Inc. Method for making a semiconductor device comprising a lattice matching layer
US7781827B2 (en) 2007-01-24 2010-08-24 Mears Technologies, Inc. Semiconductor device with a vertical MOSFET including a superlattice and related methods
US7812339B2 (en) 2007-04-23 2010-10-12 Mears Technologies, Inc. Method for making a semiconductor device including shallow trench isolation (STI) regions with maskless superlattice deposition following STI formation and related structures
US7863066B2 (en) 2007-02-16 2011-01-04 Mears Technologies, Inc. Method for making a multiple-wavelength opto-electronic device including a superlattice
US7880161B2 (en) 2007-02-16 2011-02-01 Mears Technologies, Inc. Multiple-wavelength opto-electronic device including a superlattice
US7928425B2 (en) 2007-01-25 2011-04-19 Mears Technologies, Inc. Semiconductor device including a metal-to-semiconductor superlattice interface layer and related methods
US9716147B2 (en) 2014-06-09 2017-07-25 Atomera Incorporated Semiconductor devices with enhanced deterministic doping and related methods
US9721790B2 (en) 2015-06-02 2017-08-01 Atomera Incorporated Method for making enhanced semiconductor structures in single wafer processing chamber with desired uniformity control
US9722046B2 (en) 2014-11-25 2017-08-01 Atomera Incorporated Semiconductor device including a superlattice and replacement metal gate structure and related methods
US9899479B2 (en) 2015-05-15 2018-02-20 Atomera Incorporated Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods
US9972685B2 (en) 2013-11-22 2018-05-15 Atomera Incorporated Vertical semiconductor devices including superlattice punch through stop layer and related methods
US10381242B2 (en) 2017-05-16 2019-08-13 Atomera Incorporated Method for making a semiconductor device including a superlattice as a gettering layer

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53131779A (en) * 1977-04-20 1978-11-16 Ibm Semiconductor superlattice structure
JPS55117281A (en) * 1979-03-05 1980-09-09 Nippon Telegr & Teleph Corp <Ntt> 3[5 group compound semiconductor hetero structure mosfet
JPS5984475A (ja) * 1982-11-05 1984-05-16 Hitachi Ltd 電界効果型トランジスタ

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53131779A (en) * 1977-04-20 1978-11-16 Ibm Semiconductor superlattice structure
JPS55117281A (en) * 1979-03-05 1980-09-09 Nippon Telegr & Teleph Corp <Ntt> 3[5 group compound semiconductor hetero structure mosfet
JPS5984475A (ja) * 1982-11-05 1984-05-16 Hitachi Ltd 電界効果型トランジスタ

Cited By (78)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61230374A (ja) * 1985-04-05 1986-10-14 Seiko Epson Corp 電界効果型トランジスタ及びその製造方法
JPS62279672A (ja) * 1986-05-28 1987-12-04 Kanegafuchi Chem Ind Co Ltd 半導体装置
US4806998A (en) * 1986-06-30 1989-02-21 Thomson-Csf Heterojunction and dual channel semiconductor field effect transistor or negative transconductive device
JPS6394680A (ja) * 1986-10-08 1988-04-25 Semiconductor Energy Lab Co Ltd 絶縁ゲイト型電界効果半導体装置
JPS6394681A (ja) * 1986-10-08 1988-04-25 Semiconductor Energy Lab Co Ltd 絶縁ゲイト型電界効果半導体装置の作製方法
JPS6394682A (ja) * 1986-10-08 1988-04-25 Semiconductor Energy Lab Co Ltd 絶縁ゲイト型電界効果半導体装置
US4908678A (en) * 1986-10-08 1990-03-13 Semiconductor Energy Laboratory Co., Ltd. FET with a super lattice channel
US4988634A (en) * 1986-10-08 1991-01-29 Semiconductor Energy Laboratory Co., Ltd. Method for forming FET with a super lattice channel
US5008211A (en) * 1986-10-08 1991-04-16 Semiconductor Energy Laboratory Co., Ltd. Method for forming FET with a super lattice channel
US5021839A (en) * 1986-10-08 1991-06-04 Semiconductor Energy Laboratory Co., Ltd. FET with a super lattice channel
US5051786A (en) * 1989-10-24 1991-09-24 Mcnc Passivated polycrystalline semiconductors quantum well/superlattice structures fabricated thereof
EP0694756A2 (en) 1994-07-27 1996-01-31 Shimadzu Corporation Elongation measurement using a laser non-contact extensometer
US6993222B2 (en) 1999-03-03 2006-01-31 Rj Mears, Llc Optical filter device with aperiodically arranged grating elements
US7123792B1 (en) 1999-03-05 2006-10-17 Rj Mears, Llc Configurable aperiodic grating device
US6460418B1 (en) 2000-01-19 2002-10-08 Kishimoto Sangyo Co., Ltd. Method of and apparatus for measuring elongation of a test specimen
WO2002001641A1 (en) * 2000-06-27 2002-01-03 Matsushita Electric Industrial Co., Ltd. Semiconductor device
US6674131B2 (en) 2000-06-27 2004-01-06 Matsushita Electric Industrial Co., Ltd. Semiconductor power device for high-temperature applications
WO2002043157A1 (en) * 2000-11-21 2002-05-30 Matsushita Electric Industrial Co.,Ltd. Semiconductor device and its manufacturing method
US6580125B2 (en) 2000-11-21 2003-06-17 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same
JPWO2002043157A1 (ja) * 2000-11-21 2004-04-02 松下電器産業株式会社 半導体装置およびその製造方法
AU2004300981B2 (en) * 2003-06-26 2007-10-18 Mears Technologies, Inc. Method for making semiconductor device including band-engineered superlattice
US7514328B2 (en) 2003-06-26 2009-04-07 Mears Technologies, Inc. Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween
WO2005034245A1 (en) * 2003-06-26 2005-04-14 Rj Mears, Llc Semiconductor device including band-engineered superlattice
WO2005013371A3 (en) * 2003-06-26 2005-04-14 Rj Mears Llc Semiconductor device including band-engineered superlattice
US6952018B2 (en) 2003-06-26 2005-10-04 Rj Mears, Llc Semiconductor device including band-engineered superlattice
US6958486B2 (en) 2003-06-26 2005-10-25 Rj Mears, Llc Semiconductor device including band-engineered superlattice
US7018900B2 (en) 2003-06-26 2006-03-28 Rj Mears, Llc Method for making a semiconductor device comprising a superlattice channel vertically stepped above source and drain regions
US7034329B2 (en) 2003-06-26 2006-04-25 Rj Mears, Llc Semiconductor device including band-engineered superlattice having 3/1-5/1 germanium layer structure
US7033437B2 (en) 2003-06-26 2006-04-25 Rj Mears, Llc Method for making semiconductor device including band-engineered superlattice
US7045813B2 (en) 2003-06-26 2006-05-16 Rj Mears, Llc Semiconductor device including a superlattice with regions defining a semiconductor junction
US7045377B2 (en) 2003-06-26 2006-05-16 Rj Mears, Llc Method for making a semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
US7071119B2 (en) 2003-06-26 2006-07-04 Rj Mears, Llc Method for making a semiconductor device including band-engineered superlattice having 3/1-5/1 germanium layer structure
US7109052B2 (en) 2003-06-26 2006-09-19 Rj Mears, Llc Method for making an integrated circuit comprising a waveguide having an energy band engineered superlattice
US7227174B2 (en) 2003-06-26 2007-06-05 Rj Mears, Llc Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
US7229902B2 (en) 2003-06-26 2007-06-12 Rj Mears, Llc Method for making a semiconductor device including a superlattice with regions defining a semiconductor junction
US7265002B2 (en) 2003-06-26 2007-09-04 Rj Mears, Llc Method for making a semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channel
US7279701B2 (en) 2003-06-26 2007-10-09 Rj Mears, Llc Semiconductor device comprising a superlattice with upper portions extending above adjacent upper portions of source and drain regions
US7279699B2 (en) 2003-06-26 2007-10-09 Rj Mears, Llc Integrated circuit comprising a waveguide having an energy band engineered superlattice
WO2005018005A1 (en) * 2003-06-26 2005-02-24 Rj Mears, Llc Semiconductor device including mosfet having band-engineered superlattice
AU2004306355B2 (en) * 2003-06-26 2007-10-18 Mears Technologies, Inc. Semiconductor device including band-engineered superlattice
AU2004300982B2 (en) * 2003-06-26 2007-10-25 Mears Technologies, Inc. Semiconductor device including MOSFET having band-engineered superlattice
US7288457B2 (en) 2003-06-26 2007-10-30 Rj Mears, Llc Method for making semiconductor device comprising a superlattice with upper portions extending above adjacent upper portions of source and drain regions
US7303948B2 (en) 2003-06-26 2007-12-04 Mears Technologies, Inc. Semiconductor device including MOSFET having band-engineered superlattice
US7432524B2 (en) 2003-06-26 2008-10-07 Mears Technologies, Inc. Integrated circuit comprising an active optical device having an energy band engineered superlattice
US7435988B2 (en) 2003-06-26 2008-10-14 Mears Technologies, Inc. Semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channel
US7436026B2 (en) 2003-06-26 2008-10-14 Mears Technologies, Inc. Semiconductor device comprising a superlattice channel vertically stepped above source and drain regions
US7446334B2 (en) 2003-06-26 2008-11-04 Mears Technologies, Inc. Electronic device comprising active optical devices with an energy band engineered superlattice
US7446002B2 (en) 2003-06-26 2008-11-04 Mears Technologies, Inc. Method for making a semiconductor device comprising a superlattice dielectric interface layer
US7491587B2 (en) 2003-06-26 2009-02-17 Mears Technologies, Inc. Method for making a semiconductor device having a semiconductor-on-insulator (SOI) configuration and including a superlattice on a thin semiconductor layer
WO2005018004A1 (en) * 2003-06-26 2005-02-24 Rj Mears, Llc Method for making semiconductor device including band-engineered superlattice
US7659539B2 (en) 2003-06-26 2010-02-09 Mears Technologies, Inc. Semiconductor device including a floating gate memory cell with a superlattice channel
US7531828B2 (en) 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions
US7531850B2 (en) 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including a memory cell with a negative differential resistance (NDR) device
US7531829B2 (en) 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance
US7535041B2 (en) 2003-06-26 2009-05-19 Mears Technologies, Inc. Method for making a semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance
US7586165B2 (en) 2003-06-26 2009-09-08 Mears Technologies, Inc. Microelectromechanical systems (MEMS) device including a superlattice
US7586116B2 (en) 2003-06-26 2009-09-08 Mears Technologies, Inc. Semiconductor device having a semiconductor-on-insulator configuration and a superlattice
US7598515B2 (en) 2003-06-26 2009-10-06 Mears Technologies, Inc. Semiconductor device including a strained superlattice and overlying stress layer and related methods
US7612366B2 (en) 2003-06-26 2009-11-03 Mears Technologies, Inc. Semiconductor device including a strained superlattice layer above a stress layer
US7517702B2 (en) 2005-12-22 2009-04-14 Mears Technologies, Inc. Method for making an electronic device including a poled superlattice having a net electrical dipole moment
US7700447B2 (en) 2006-02-21 2010-04-20 Mears Technologies, Inc. Method for making a semiconductor device comprising a lattice matching layer
US7718996B2 (en) 2006-02-21 2010-05-18 Mears Technologies, Inc. Semiconductor device comprising a lattice matching layer
US7781827B2 (en) 2007-01-24 2010-08-24 Mears Technologies, Inc. Semiconductor device with a vertical MOSFET including a superlattice and related methods
US7928425B2 (en) 2007-01-25 2011-04-19 Mears Technologies, Inc. Semiconductor device including a metal-to-semiconductor superlattice interface layer and related methods
US8389974B2 (en) 2007-02-16 2013-03-05 Mears Technologies, Inc. Multiple-wavelength opto-electronic device including a superlattice
US7863066B2 (en) 2007-02-16 2011-01-04 Mears Technologies, Inc. Method for making a multiple-wavelength opto-electronic device including a superlattice
US7880161B2 (en) 2007-02-16 2011-02-01 Mears Technologies, Inc. Multiple-wavelength opto-electronic device including a superlattice
US7812339B2 (en) 2007-04-23 2010-10-12 Mears Technologies, Inc. Method for making a semiconductor device including shallow trench isolation (STI) regions with maskless superlattice deposition following STI formation and related structures
US9972685B2 (en) 2013-11-22 2018-05-15 Atomera Incorporated Vertical semiconductor devices including superlattice punch through stop layer and related methods
US9716147B2 (en) 2014-06-09 2017-07-25 Atomera Incorporated Semiconductor devices with enhanced deterministic doping and related methods
US10170560B2 (en) 2014-06-09 2019-01-01 Atomera Incorporated Semiconductor devices with enhanced deterministic doping and related methods
US9722046B2 (en) 2014-11-25 2017-08-01 Atomera Incorporated Semiconductor device including a superlattice and replacement metal gate structure and related methods
US10084045B2 (en) 2014-11-25 2018-09-25 Atomera Incorporated Semiconductor device including a superlattice and replacement metal gate structure and related methods
US9899479B2 (en) 2015-05-15 2018-02-20 Atomera Incorporated Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods
US9941359B2 (en) 2015-05-15 2018-04-10 Atomera Incorporated Semiconductor devices with superlattice and punch-through stop (PTS) layers at different depths and related methods
US9721790B2 (en) 2015-06-02 2017-08-01 Atomera Incorporated Method for making enhanced semiconductor structures in single wafer processing chamber with desired uniformity control
US10381242B2 (en) 2017-05-16 2019-08-13 Atomera Incorporated Method for making a semiconductor device including a superlattice as a gettering layer
US10410880B2 (en) 2017-05-16 2019-09-10 Atomera Incorporated Semiconductor device including a superlattice as a gettering layer

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