JPH0719888B2
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1985-04-05 |
1995-03-06 |
セイコーエプソン株式会社 |
電界効果型トランジスタ及びその製造方法
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JPS62279672A
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1986-05-28 |
1987-12-04 |
Kanegafuchi Chem Ind Co Ltd |
半導体装置
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FR2600821B1
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1986-06-30 |
1988-12-30 |
Thomson Csf |
Dispositif semi-conducteur a heterojonction et double canal, son application a un transistor a effet de champ, et son application a un dispositif de transductance negative
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JP2709374B2
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1986-10-08 |
1998-02-04 |
株式会社 半導体エネルギー研究所 |
絶縁ゲイト型電界効果半導体装置
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JPS6394681A
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1986-10-08 |
1988-04-25 |
Semiconductor Energy Lab Co Ltd |
絶縁ゲイト型電界効果半導体装置の作製方法
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1986-10-08 |
1990-03-13 |
Semiconductor Energy Laboratory Co., Ltd. |
FET with a super lattice channel
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JPS6394682A
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1986-10-08 |
1988-04-25 |
Semiconductor Energy Lab Co Ltd |
絶縁ゲイト型電界効果半導体装置
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1989-10-24 |
1991-09-24 |
Mcnc |
Passivated polycrystalline semiconductors quantum well/superlattice structures fabricated thereof
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JP2692599B2
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1994-07-27 |
1997-12-17 |
株式会社島津製作所 |
レーザー非接触伸び計
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1999-03-03 |
2006-01-31 |
Rj Mears, Llc |
Optical filter device with aperiodically arranged grating elements
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1999-03-05 |
2003-09-10 |
Nanovis Llc |
Superlattices
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JP3373831B2
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2000-01-19 |
2003-02-04 |
岸本産業株式会社 |
試験片の伸び測定方法及び装置
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2000-06-27 |
2008-10-08 |
Matsushita Electric Ind Co Ltd |
SEMICONDUCTOR COMPONENT
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2000-11-21 |
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2003-06-26 |
2005-02-24 |
Rj Mears, Llc |
Semiconductor device including mosfet having band-engineered superlattice
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2003-06-26 |
2006-05-16 |
Rj Mears, Llc |
Method for making a semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
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2003-06-26 |
2007-06-12 |
Rj Mears, Llc |
Method for making a semiconductor device including a superlattice with regions defining a semiconductor junction
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2003-06-26 |
2009-09-08 |
Mears Technologies, Inc. |
Microelectromechanical systems (MEMS) device including a superlattice
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2003-06-26 |
2009-05-12 |
Mears Technologies, Inc. |
Semiconductor device including a memory cell with a negative differential resistance (NDR) device
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2003-06-26 |
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Mears Technologies, Inc. |
Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions
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2003-06-26 |
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Mears Technologies, Inc. |
Method for making a semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance
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2003-06-26 |
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Mears Technologies, Inc. |
Method for making a semiconductor device having a semiconductor-on-insulator (SOI) configuration and including a superlattice on a thin semiconductor layer
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2003-06-26 |
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Semiconductor device including a floating gate memory cell with a superlattice channel
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Method for making semiconductor device including band-engineered superlattice
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2003-06-26 |
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Semiconductor device including MOSFET having band-engineered superlattice
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2003-06-26 |
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Mears Technologies, Inc. |
Semiconductor device having a semiconductor-on-insulator configuration and a superlattice
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2003-06-26 |
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Mears Technologies, Inc. |
Semiconductor device including a strained superlattice and overlying stress layer and related methods
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2003-06-26 |
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Mears Technologies, Inc. |
Semiconductor device including a strained superlattice layer above a stress layer
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2003-06-26 |
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Mears Technologies, Inc. |
Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween
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2003-06-26 |
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Mears Technologies, Inc. |
Method for making a semiconductor device comprising a superlattice dielectric interface layer
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Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
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2003-06-26 |
2006-05-16 |
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Semiconductor device including a superlattice with regions defining a semiconductor junction
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Semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance
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Method for making an electronic device including a poled superlattice having a net electrical dipole moment
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Mears Technologies, Inc. |
Semiconductor device comprising a lattice matching layer and associated methods
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Semiconductor device with a vertical MOSFET including a superlattice and related methods
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Semiconductor device including a metal-to-semiconductor superlattice interface layer and related methods
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Mears Technologies, Inc. |
Method for making a multiple-wavelength opto-electronic device including a superlattice
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2007-02-16 |
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Multiple-wavelength opto-electronic device including a superlattice
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Method for making a semiconductor device including shallow trench isolation (STI) regions with maskless superlattice deposition following STI formation and related structures
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2013-11-22 |
2020-06-16 |
阿托梅拉公司 |
包括超晶格穿通停止层堆叠的垂直半导体装置和相关方法
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2014-06-09 |
2017-07-25 |
Atomera Incorporated |
Semiconductor devices with enhanced deterministic doping and related methods
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2014-11-25 |
2017-08-01 |
Atomera Incorporated |
Semiconductor device including a superlattice and replacement metal gate structure and related methods
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2015-05-15 |
2021-11-03 |
Atomera Incorporated |
Method of fabricating semiconductor devices with superlattice and punch-through stop (pts) layers at different depths
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2015-06-02 |
2017-08-01 |
Atomera Incorporated |
Method for making enhanced semiconductor structures in single wafer processing chamber with desired uniformity control
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2017-05-16 |
2022-08-10 |
Atomera Incorporated |
Semiconductor device and method including a superlattice as a gettering layer
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