JPS6057159B2 - Ｍｏｓ半導体記憶器 - Google Patents
Ｍｏｓ半導体記憶器Info
- Publication number
- JPS6057159B2 JPS6057159B2 JP52125635A JP12563577A JPS6057159B2 JP S6057159 B2 JPS6057159 B2 JP S6057159B2 JP 52125635 A JP52125635 A JP 52125635A JP 12563577 A JP12563577 A JP 12563577A JP S6057159 B2 JPS6057159 B2 JP S6057159B2
- Authority
- JP
- Japan
- Prior art keywords
- evaluation circuit
- bit line
- memory
- storage
- bit lines
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 238000011156 evaluation Methods 0.000 claims description 85
- 210000000352 storage cell Anatomy 0.000 claims description 61
- 210000004027 cell Anatomy 0.000 claims description 55
- 239000003990 capacitor Substances 0.000 description 16
- 238000010586 diagram Methods 0.000 description 14
- 238000000034 method Methods 0.000 description 12
- 230000008569 process Effects 0.000 description 12
- 101100030351 Schizosaccharomyces pombe (strain 972 / ATCC 24843) dis2 gene Proteins 0.000 description 3
- 230000000295 complement effect Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000008929 regeneration Effects 0.000 description 2
- 238000011069 regeneration method Methods 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE2647394.9 | 1976-10-20 | ||
| DE2647394A DE2647394C2 (de) | 1976-10-20 | 1976-10-20 | MOS-Halbleiterspeicherbaustein |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5350944A JPS5350944A (en) | 1978-05-09 |
| JPS6057159B2 true JPS6057159B2 (ja) | 1985-12-13 |
Family
ID=5990933
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP52125635A Expired JPS6057159B2 (ja) | 1976-10-20 | 1977-10-19 | Ｍｏｓ半導体記憶器 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4122546A (Direct) |
| JP (1) | JPS6057159B2 (Direct) |
| DE (1) | DE2647394C2 (Direct) |
| FR (1) | FR2368783A1 (Direct) |
| GB (1) | GB1593866A (Direct) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3025103U (ja) * | 1995-11-22 | 1996-06-11 | 株式会社マックエイト | 電子部品の印刷配線板への取付構造 |
Families Citing this family (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54148340A (en) * | 1978-05-12 | 1979-11-20 | Nec Corp | Memory circuit |
| JPS5817998B2 (ja) * | 1978-10-26 | 1983-04-11 | 富士通株式会社 | 半導体メモリ |
| JPS5558890A (en) * | 1978-10-27 | 1980-05-01 | Hitachi Ltd | Reference voltage generation circuit |
| DE2855118C2 (de) * | 1978-12-20 | 1981-03-26 | IBM Deutschland GmbH, 70569 Stuttgart | Dynamischer FET-Speicher |
| DE2904994C2 (de) * | 1979-02-09 | 1984-02-16 | Siemens AG, 1000 Berlin und 8000 München | MOS-Halbleiterspeicherbaustein mit sich kreuzenden Wort- und Bitleitungen |
| DE2926514A1 (de) * | 1979-06-30 | 1981-01-15 | Ibm Deutschland | Elektrische speicheranordnung und verfahren zu ihrem betrieb |
| JPS5683891A (en) * | 1979-12-13 | 1981-07-08 | Fujitsu Ltd | Semiconductor storage device |
| US4287576A (en) * | 1980-03-26 | 1981-09-01 | International Business Machines Corporation | Sense amplifying system for memories with small cells |
| USRE32682E (en) * | 1980-10-10 | 1988-05-31 | Inmos Corporation | Folded bit line-shared sense amplifiers |
| US4351034A (en) * | 1980-10-10 | 1982-09-21 | Inmos Corporation | Folded bit line-shared sense amplifiers |
| DE3101802A1 (de) * | 1981-01-21 | 1982-08-19 | Siemens AG, 1000 Berlin und 8000 München | Monolithisch integrierter halbleiterspeicher |
| JPS57198592A (en) * | 1981-05-29 | 1982-12-06 | Hitachi Ltd | Semiconductor memory device |
| JPS58111183A (ja) * | 1981-12-25 | 1983-07-02 | Hitachi Ltd | ダイナミツクｒａｍ集積回路装置 |
| JPS60234295A (ja) * | 1984-05-04 | 1985-11-20 | Fujitsu Ltd | 半導体記憶装置 |
| KR900005667B1 (ko) * | 1984-11-20 | 1990-08-03 | 후지쓰 가부시끼가이샤 | 반도체 기억장치 |
| JPS61178795A (ja) * | 1985-02-01 | 1986-08-11 | Toshiba Corp | ダイナミツク型半導体記憶装置 |
| JPS61296598A (ja) * | 1985-06-21 | 1986-12-27 | Mitsubishi Electric Corp | Ｍｏｓダイナミツクｒａｍのダミ−ワ−ド線駆動回路 |
| JPS6282597A (ja) * | 1985-10-08 | 1987-04-16 | Fujitsu Ltd | 半導体記憶装置 |
| JPS62197992A (ja) * | 1986-02-25 | 1987-09-01 | Mitsubishi Electric Corp | ダイナミツクｒａｍ |
| JPS62200596A (ja) * | 1986-02-26 | 1987-09-04 | Mitsubishi Electric Corp | 半導体メモリ |
| JPH07111823B2 (ja) * | 1986-03-18 | 1995-11-29 | 三菱電機株式会社 | 半導体記憶装置 |
| US4731747A (en) * | 1986-04-14 | 1988-03-15 | American Telephone And Telegraph Company, At&T Bell Laboratories | Highly parallel computation network with normalized speed of response |
| JPH07107797B2 (ja) * | 1987-02-10 | 1995-11-15 | 三菱電機株式会社 | ダイナミツクランダムアクセスメモリ |
| JPS63146295A (ja) * | 1987-11-18 | 1988-06-18 | Toshiba Corp | 半導体メモリ |
| JP2566517B2 (ja) * | 1993-04-28 | 1996-12-25 | 三菱電機株式会社 | ダイナミック型半導体記憶装置 |
| TWI291699B (en) * | 2005-05-26 | 2007-12-21 | Macronix Int Co Ltd | Method of reading the bits of nitride read-only memory cell |
| KR102160178B1 (ko) * | 2016-08-31 | 2020-09-28 | 마이크론 테크놀로지, 인크 | 메모리 어레이 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3983545A (en) * | 1975-06-30 | 1976-09-28 | International Business Machines Corporation | Random access memory employing single ended sense latch for one device cell |
-
1976
- 1976-10-20 DE DE2647394A patent/DE2647394C2/de not_active Expired
-
1977
- 1977-09-27 US US05/837,201 patent/US4122546A/en not_active Expired - Lifetime
- 1977-10-18 FR FR7731288A patent/FR2368783A1/fr active Granted
- 1977-10-19 JP JP52125635A patent/JPS6057159B2/ja not_active Expired
- 1977-10-19 GB GB43446/77A patent/GB1593866A/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3025103U (ja) * | 1995-11-22 | 1996-06-11 | 株式会社マックエイト | 電子部品の印刷配線板への取付構造 |
Also Published As
| Publication number | Publication date |
|---|---|
| DE2647394B1 (de) | 1978-03-16 |
| FR2368783A1 (fr) | 1978-05-19 |
| FR2368783B1 (Direct) | 1984-05-04 |
| DE2647394C2 (de) | 1978-11-16 |
| US4122546A (en) | 1978-10-24 |
| GB1593866A (en) | 1981-07-22 |
| JPS5350944A (en) | 1978-05-09 |
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