JPS6045089A - 回路配線用基板 - Google Patents

回路配線用基板

Info

Publication number
JPS6045089A
JPS6045089A JP58153511A JP15351183A JPS6045089A JP S6045089 A JPS6045089 A JP S6045089A JP 58153511 A JP58153511 A JP 58153511A JP 15351183 A JP15351183 A JP 15351183A JP S6045089 A JPS6045089 A JP S6045089A
Authority
JP
Japan
Prior art keywords
layer
plating layer
copper foil
thickness
circuit wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58153511A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0158860B2 (enrdf_load_stackoverflow
Inventor
瑛一 綱島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP58153511A priority Critical patent/JPS6045089A/ja
Publication of JPS6045089A publication Critical patent/JPS6045089A/ja
Publication of JPH0158860B2 publication Critical patent/JPH0158860B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Parts Printed On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)
JP58153511A 1983-08-22 1983-08-22 回路配線用基板 Granted JPS6045089A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58153511A JPS6045089A (ja) 1983-08-22 1983-08-22 回路配線用基板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58153511A JPS6045089A (ja) 1983-08-22 1983-08-22 回路配線用基板

Publications (2)

Publication Number Publication Date
JPS6045089A true JPS6045089A (ja) 1985-03-11
JPH0158860B2 JPH0158860B2 (enrdf_load_stackoverflow) 1989-12-13

Family

ID=15564137

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58153511A Granted JPS6045089A (ja) 1983-08-22 1983-08-22 回路配線用基板

Country Status (1)

Country Link
JP (1) JPS6045089A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6453918A (en) * 1987-08-25 1989-03-01 Mutou Kk Substance assortment method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55150292A (en) * 1979-05-11 1980-11-22 Fujitsu Ltd Method of fabricating printed circuit board
JPS5815905A (ja) * 1982-06-15 1983-01-29 Ichimaru Fuarukosu Kk 可溶化シルクペプチド含有皮膚化粧料
JPS5852836A (ja) * 1981-09-24 1983-03-29 Fuji Electric Co Ltd 複合集積回路

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55150292A (en) * 1979-05-11 1980-11-22 Fujitsu Ltd Method of fabricating printed circuit board
JPS5852836A (ja) * 1981-09-24 1983-03-29 Fuji Electric Co Ltd 複合集積回路
JPS5815905A (ja) * 1982-06-15 1983-01-29 Ichimaru Fuarukosu Kk 可溶化シルクペプチド含有皮膚化粧料

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6453918A (en) * 1987-08-25 1989-03-01 Mutou Kk Substance assortment method

Also Published As

Publication number Publication date
JPH0158860B2 (enrdf_load_stackoverflow) 1989-12-13

Similar Documents

Publication Publication Date Title
US4993148A (en) Method of manufacturing a circuit board
JPH0697225A (ja) 半導体装置
JPH10270624A (ja) チップサイズパッケージ及びその製造方法
JP3952129B2 (ja) 半導体装置、実装基板及びその製造方法、回路基板並びに電子機器
JP3482850B2 (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
JPS6127089Y2 (enrdf_load_stackoverflow)
JPS6045089A (ja) 回路配線用基板
JPH1074859A (ja) Qfn半導体パッケージ
JPH10125817A (ja) 2層配線基板
JP2652222B2 (ja) 電子部品搭載用基板
JP2787230B2 (ja) 電子部品塔載用基板
JPH05235498A (ja) 突起電極付プリント回路基板および接合方法
JPH0735389Y2 (ja) 半導体装置
JP2784209B2 (ja) 半導体装置
JPS59215753A (ja) 回路部品の封止方法
JP2000133745A (ja) 半導体装置
JPH05327156A (ja) プリント回路基板
JPS6149499A (ja) フレキシブル多層配線基板
JPS6293993A (ja) 電子回路装置とその実装方法
JPH08274123A (ja) 混成集積回路基板用導体の製造方法
JPH05259221A (ja) 電子部品搭載装置
JP4396862B2 (ja) 半導体装置、回路基板および電子機器
JPH1012987A (ja) 2層配線基板
JPH10209593A (ja) 2層配線基板、及びその製造方法
JPS59204298A (ja) 印刷回路板の形成方法