JPS60206058A - 多層半導体装置の製造方法 - Google Patents

多層半導体装置の製造方法

Info

Publication number
JPS60206058A
JPS60206058A JP59060943A JP6094384A JPS60206058A JP S60206058 A JPS60206058 A JP S60206058A JP 59060943 A JP59060943 A JP 59060943A JP 6094384 A JP6094384 A JP 6094384A JP S60206058 A JPS60206058 A JP S60206058A
Authority
JP
Japan
Prior art keywords
substrate
multilayer
semiconductor
semiconductor wafer
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59060943A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0520906B2 (https=
Inventor
Takashi Kato
隆 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59060943A priority Critical patent/JPS60206058A/ja
Publication of JPS60206058A publication Critical patent/JPS60206058A/ja
Publication of JPH0520906B2 publication Critical patent/JPH0520906B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/834—Interconnections on sidewalls of chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips

Landscapes

  • Mechanical Treatment Of Semiconductor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP59060943A 1984-03-30 1984-03-30 多層半導体装置の製造方法 Granted JPS60206058A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59060943A JPS60206058A (ja) 1984-03-30 1984-03-30 多層半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59060943A JPS60206058A (ja) 1984-03-30 1984-03-30 多層半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS60206058A true JPS60206058A (ja) 1985-10-17
JPH0520906B2 JPH0520906B2 (https=) 1993-03-22

Family

ID=13156963

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59060943A Granted JPS60206058A (ja) 1984-03-30 1984-03-30 多層半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS60206058A (https=)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6453440A (en) * 1987-08-25 1989-03-01 Hitachi Ltd Three-dimensional semiconductor integrated circuit device
EP1041624A1 (en) * 1999-04-02 2000-10-04 Interuniversitair Microelektronica Centrum Vzw Method of transferring ultra-thin substrates and application of the method to the manufacture of a multilayer thin film device
WO2009025974A3 (en) * 2007-08-16 2009-05-07 Micron Technology Inc Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods
DE102009004168A1 (de) 2008-01-11 2009-07-16 Disco Corp. Schichtbauelement-Herstellungsverfahren
US7692931B2 (en) 2006-07-17 2010-04-06 Micron Technology, Inc. Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods
JP2010183058A (ja) * 2009-02-06 2010-08-19 Headway Technologies Inc 積層チップパッケージおよびその製造方法
JP2010534951A (ja) * 2007-07-27 2010-11-11 テッセラ，インコーポレイテッド 適用後パッド延在部を伴う再構成ウエハ積層パッケージング
JP2010536171A (ja) * 2007-08-03 2010-11-25 テセラ・テクノロジーズ・ハンガリー・ケイエフティー 再生ウェーハを使用する積層型パッケージ
US7843050B2 (en) 2007-07-24 2010-11-30 Micron Technology, Inc. Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
US7858497B2 (en) 2008-10-22 2010-12-28 Disco Corporation Stacked device manufacturing method

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6453440A (en) * 1987-08-25 1989-03-01 Hitachi Ltd Three-dimensional semiconductor integrated circuit device
EP1041624A1 (en) * 1999-04-02 2000-10-04 Interuniversitair Microelektronica Centrum Vzw Method of transferring ultra-thin substrates and application of the method to the manufacture of a multilayer thin film device
US7692931B2 (en) 2006-07-17 2010-04-06 Micron Technology, Inc. Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods
US8869387B2 (en) 2006-07-17 2014-10-28 Micron Technology, Inc. Methods for making microelectronic die systems
US8198720B2 (en) 2007-07-24 2012-06-12 Micron Technology, Inc. Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
US10056359B2 (en) 2007-07-24 2018-08-21 Micron Technology, Inc. Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
US9653444B2 (en) 2007-07-24 2017-05-16 Micron Technology, Inc. Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
US9165910B2 (en) 2007-07-24 2015-10-20 Micron Technology, Inc. Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
US8906744B2 (en) 2007-07-24 2014-12-09 Micron Technology, Inc. Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
US7843050B2 (en) 2007-07-24 2010-11-30 Micron Technology, Inc. Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
JP2010534951A (ja) * 2007-07-27 2010-11-11 テッセラ，インコーポレイテッド 適用後パッド延在部を伴う再構成ウエハ積層パッケージング
JP2010536171A (ja) * 2007-08-03 2010-11-25 テセラ・テクノロジーズ・ハンガリー・ケイエフティー 再生ウェーハを使用する積層型パッケージ
US7947529B2 (en) 2007-08-16 2011-05-24 Micron Technology, Inc. Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods
WO2009025974A3 (en) * 2007-08-16 2009-05-07 Micron Technology Inc Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods
TWI485762B (zh) * 2008-01-11 2015-05-21 迪思科股份有限公司 The manufacturing method of the laminated apparatus
US7687375B2 (en) 2008-01-11 2010-03-30 Disco Corporation Lamination device manufacturing method
DE102009004168A1 (de) 2008-01-11 2009-07-16 Disco Corp. Schichtbauelement-Herstellungsverfahren
US7858497B2 (en) 2008-10-22 2010-12-28 Disco Corporation Stacked device manufacturing method
JP2010183058A (ja) * 2009-02-06 2010-08-19 Headway Technologies Inc 積層チップパッケージおよびその製造方法

Also Published As

Publication number Publication date
JPH0520906B2 (https=) 1993-03-22

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