JPH0520906B2 - - Google Patents

Info

Publication number
JPH0520906B2
JPH0520906B2 JP59060943A JP6094384A JPH0520906B2 JP H0520906 B2 JPH0520906 B2 JP H0520906B2 JP 59060943 A JP59060943 A JP 59060943A JP 6094384 A JP6094384 A JP 6094384A JP H0520906 B2 JPH0520906 B2 JP H0520906B2
Authority
JP
Japan
Prior art keywords
semiconductor
multilayer
semiconductor wafer
wafers
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59060943A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60206058A (ja
Inventor
Takashi Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59060943A priority Critical patent/JPS60206058A/ja
Publication of JPS60206058A publication Critical patent/JPS60206058A/ja
Publication of JPH0520906B2 publication Critical patent/JPH0520906B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/834—Interconnections on sidewalls of chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips

Landscapes

  • Mechanical Treatment Of Semiconductor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP59060943A 1984-03-30 1984-03-30 多層半導体装置の製造方法 Granted JPS60206058A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59060943A JPS60206058A (ja) 1984-03-30 1984-03-30 多層半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59060943A JPS60206058A (ja) 1984-03-30 1984-03-30 多層半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS60206058A JPS60206058A (ja) 1985-10-17
JPH0520906B2 true JPH0520906B2 (https=) 1993-03-22

Family

ID=13156963

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59060943A Granted JPS60206058A (ja) 1984-03-30 1984-03-30 多層半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS60206058A (https=)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6453440A (en) * 1987-08-25 1989-03-01 Hitachi Ltd Three-dimensional semiconductor integrated circuit device
EP1041624A1 (en) * 1999-04-02 2000-10-04 Interuniversitair Microelektronica Centrum Vzw Method of transferring ultra-thin substrates and application of the method to the manufacture of a multilayer thin film device
SG139573A1 (en) 2006-07-17 2008-02-29 Micron Technology Inc Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods
SG149726A1 (en) 2007-07-24 2009-02-27 Micron Technology Inc Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
CN101809739B (zh) * 2007-07-27 2014-08-20 泰塞拉公司 具有后应用的衬垫延长部分的重构晶片堆封装
CN101861646B (zh) * 2007-08-03 2015-03-18 泰塞拉公司 利用再生晶圆的堆叠封装
SG150396A1 (en) 2007-08-16 2009-03-30 Micron Technology Inc Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods
JP5296386B2 (ja) 2008-01-11 2013-09-25 株式会社ディスコ 積層デバイスの製造方法
JP5221279B2 (ja) 2008-10-22 2013-06-26 株式会社ディスコ 積層デバイスの製造方法
US7968374B2 (en) * 2009-02-06 2011-06-28 Headway Technologies, Inc. Layered chip package with wiring on the side surfaces

Also Published As

Publication number Publication date
JPS60206058A (ja) 1985-10-17

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