JPS5995643U - 半導体装置 - Google Patents
半導体装置Info
- Publication number
- JPS5995643U JPS5995643U JP1982191900U JP19190082U JPS5995643U JP S5995643 U JPS5995643 U JP S5995643U JP 1982191900 U JP1982191900 U JP 1982191900U JP 19190082 U JP19190082 U JP 19190082U JP S5995643 U JPS5995643 U JP S5995643U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor equipment
- lead frame
- insulating substrate
- fixed
- heat sink
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
め要約のデータは記録されません。
Description
第1図は従来の放熱板絶縁型サーイリスタあ概略平面図
、第2図は第1図のIF−IF線の断面矢視図、第3図
ないし第5図はこの考案に係る一実施例の放熱板絶縁型
サイリスタの組立工程を示す概略側面図、第6図はこの
考案に係る他の実施例の放熱板絶縁型サイリスタの概略
側面図である。 。 11・・・半導体ペレット、12・・・リードフレーム
、12b、12C・・・ボンディング部、13・・・絶
縁基板、14・・・放熱板、15・・・ワイヤ、16・
・・リードフレーム、16b、16C・・・ボンディン
グ部。
、第2図は第1図のIF−IF線の断面矢視図、第3図
ないし第5図はこの考案に係る一実施例の放熱板絶縁型
サイリスタの組立工程を示す概略側面図、第6図はこの
考案に係る他の実施例の放熱板絶縁型サイリスタの概略
側面図である。 。 11・・・半導体ペレット、12・・・リードフレーム
、12b、12C・・・ボンディング部、13・・・絶
縁基板、14・・・放熱板、15・・・ワイヤ、16・
・・リードフレーム、16b、16C・・・ボンディン
グ部。
Claims (1)
- 半導体ペレットを固着したリードフレームと放熱板との
間に絶縁基板が介挿され、リードフレームのワイヤボン
ディング部が上記絶縁基板に当接固定されたことを特徴
とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1982191900U JPS5995643U (ja) | 1982-12-17 | 1982-12-17 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1982191900U JPS5995643U (ja) | 1982-12-17 | 1982-12-17 | 半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5995643U true JPS5995643U (ja) | 1984-06-28 |
Family
ID=30413127
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1982191900U Pending JPS5995643U (ja) | 1982-12-17 | 1982-12-17 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5995643U (ja) |
-
1982
- 1982-12-17 JP JP1982191900U patent/JPS5995643U/ja active Pending
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