JPS6134750U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS6134750U
JPS6134750U JP1984121279U JP12127984U JPS6134750U JP S6134750 U JPS6134750 U JP S6134750U JP 1984121279 U JP1984121279 U JP 1984121279U JP 12127984 U JP12127984 U JP 12127984U JP S6134750 U JPS6134750 U JP S6134750U
Authority
JP
Japan
Prior art keywords
semiconductor equipment
metal film
package
insulating layer
mounting part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984121279U
Other languages
English (en)
Inventor
芳太郎 家本
Original Assignee
ロ−ム株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ロ−ム株式会社 filed Critical ロ−ム株式会社
Priority to JP1984121279U priority Critical patent/JPS6134750U/ja
Publication of JPS6134750U publication Critical patent/JPS6134750U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】 第１図はこの考案の一実施例を示す断面図、第２図はパ
ッケージを省略した平面図である。 １・・・フレーム、１・・・搭載部分、２・・・チップ
、４・・・パッケージ、５・・・絶縁層、６・・・金属
膜。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体チップを表面に搭載する搭載部分の裏面に、耐熱
    性の絶縁層を介して金属膜を設け、前記金属膜が表面に
    露出するように樹脂モールドによりパッケージを構成し
    てなる半導体装置。
JP1984121279U 1984-08-06 1984-08-06 半導体装置 Pending JPS6134750U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984121279U JPS6134750U (ja) 1984-08-06 1984-08-06 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984121279U JPS6134750U (ja) 1984-08-06 1984-08-06 半導体装置

Publications (1)

Publication Number Publication Date
JPS6134750U true JPS6134750U (ja) 1986-03-03

Family

ID=30680067

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984121279U Pending JPS6134750U (ja) 1984-08-06 1984-08-06 半導体装置

Country Status (1)

Country Link
JP (1) JPS6134750U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014013931A (ja) * 2013-09-12 2014-01-23 Denso Corp 半導体パッケージ

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014013931A (ja) * 2013-09-12 2014-01-23 Denso Corp 半導体パッケージ

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