JPS6134750U - 半導体装置 - Google Patents
半導体装置Info
- Publication number
- JPS6134750U JPS6134750U JP12127984U JP12127984U JPS6134750U JP S6134750 U JPS6134750 U JP S6134750U JP 12127984 U JP12127984 U JP 12127984U JP 12127984 U JP12127984 U JP 12127984U JP S6134750 U JPS6134750 U JP S6134750U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor equipment
- metal film
- package
- insulating layer
- mounting part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
め要約のデータは記録されません。
Description
【図面の簡単な説明】
第１図はこの考案の一実施例を示す断面図、第２図はパ
ッケージを省略した平面図である。 １・・・フレーム、１・・・搭載部分、２・・・チップ
、４・・・パッケージ、５・・・絶縁層、６・・・金属
膜。
ッケージを省略した平面図である。 １・・・フレーム、１・・・搭載部分、２・・・チップ
、４・・・パッケージ、５・・・絶縁層、６・・・金属
膜。
Claims (1)
- 半導体チップを表面に搭載する搭載部分の裏面に、耐熱
性の絶縁層を介して金属膜を設け、前記金属膜が表面に
露出するように樹脂モールドによりパッケージを構成し
てなる半導体装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12127984U JPS6134750U (ja) | 1984-08-06 | 1984-08-06 | 半導体装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12127984U JPS6134750U (ja) | 1984-08-06 | 1984-08-06 | 半導体装置 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6134750U true JPS6134750U (ja) | 1986-03-03 |
Family
ID=30680067
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12127984U Pending JPS6134750U (ja) | 1984-08-06 | 1984-08-06 | 半導体装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6134750U (ja) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014013931A (ja) * | 2013-09-12 | 2014-01-23 | Denso Corp | 半導体パッケージ |
-
1984
- 1984-08-06 JP JP12127984U patent/JPS6134750U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014013931A (ja) * | 2013-09-12 | 2014-01-23 | Denso Corp | 半導体パッケージ |
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