JPS58166051U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS58166051U
JPS58166051U JP6424882U JP6424882U JPS58166051U JP S58166051 U JPS58166051 U JP S58166051U JP 6424882 U JP6424882 U JP 6424882U JP 6424882 U JP6424882 U JP 6424882U JP S58166051 U JPS58166051 U JP S58166051U
Authority
JP
Japan
Prior art keywords
semiconductor device
pellet
lead frame
metal
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6424882U
Other languages
English (en)
Other versions
JPS6234452Y2 (ja
Inventor
増田　富三
Original Assignee
日本電気ホームエレクトロニクス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気ホームエレクトロニクス株式会社 filed Critical 日本電気ホームエレクトロニクス株式会社
Priority to JP6424882U priority Critical patent/JPS58166051U/ja
Publication of JPS58166051U publication Critical patent/JPS58166051U/ja
Application granted granted Critical
Publication of JPS6234452Y2 publication Critical patent/JPS6234452Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図及び第２図は、従来の半導体装置のリードフレー
ムの平面図及び側面図、第３図はこの考案の一実施例を
示す半導体装置のペレットマウント配線構体の平面図、
第４図はそのＹ−Ｙ線に関する断面図、第５図はその他
の実施例を示す半導体装置の断面図である。 ４・・・・・・外部導出リード、５・・・・・・リード
フレーム、１３・・・・・・基板、１５・・・・・・ペ
レット、１９・・・・・・樹脂。

Claims (1)

    【実用新案登録請求の範囲】
  1. 基板部と電極の外部導出リード部とからなるリードフレ
    ームの基板部にペレット′を固着し、少くともペレット
    を囲む部分を樹脂モールド被覆する半導体装置において
    、熱容量が十分かつ表面保護膜形成が容易な金属よりな
    る基板部と、熱伝導性が良好な金属よりなる外部導出リ
    ードとを、クラッド接合させたリードフレームを用いた
    ことを特徴とする半導体装置。
JP6424882U 1982-04-30 1982-04-30 半導体装置 Granted JPS58166051U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6424882U JPS58166051U (ja) 1982-04-30 1982-04-30 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6424882U JPS58166051U (ja) 1982-04-30 1982-04-30 半導体装置

Publications (2)

Publication Number Publication Date
JPS58166051U true JPS58166051U (ja) 1983-11-05
JPS6234452Y2 JPS6234452Y2 (ja) 1987-09-02

Family

ID=30074288

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6424882U Granted JPS58166051U (ja) 1982-04-30 1982-04-30 半導体装置

Country Status (1)

Country Link
JP (1) JPS58166051U (ja)

Also Published As

Publication number Publication date
JPS6234452Y2 (ja) 1987-09-02

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