JPS5895655U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS5895655U
JPS5895655U JP19211281U JP19211281U JPS5895655U JP S5895655 U JPS5895655 U JP S5895655U JP 19211281 U JP19211281 U JP 19211281U JP 19211281 U JP19211281 U JP 19211281U JP S5895655 U JPS5895655 U JP S5895655U
Authority
JP
Japan
Prior art keywords
header
semiconductor chip
lead frame
semiconductor equipment
wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19211281U
Other languages
English (en)
Inventor
依田　和光
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP19211281U priority Critical patent/JPS5895655U/ja
Publication of JPS5895655U publication Critical patent/JPS5895655U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図ａ、　　ｂは従来の電力用半導体装置の一例の樹
脂封止前の平面図及び側面図、第２図は第１図ａ、　ｂ
に示す電力用半導体装置の樹脂封止後の側面図、第３図
は本考案の第１の実施例の断面図、第４図は本考案の第
２の実施例の断面図である。 １・・・・・・ヘッダ一部、２・・・・・・外部リード
線、３・・・・・・半導体チップ、４・・・・・・金属
細線、５・・・・・・樹脂、１１・・・・・・ヘッダ一
部、１２・・・・・・外部リード線、１５・・・・・・
樹脂、１６．１７・・・・・・放熱ブロック。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体チップを搭載するヘッダ一部と外部リード線とが
    同一材料で同一厚さに形成されたリードフレームと、前
    記ヘッダ一部の半導体チップ搭載面と反対側の面に接触
    し、該接触面がその反対側の露出面となる表面より大き
    くなるように形成された放熱ブロックと、前記ヘッダ一
    部に搭載され前記リードフレームと結線接続される半導
    体チップと、前記放熱ブロックの露出面及び外部リード
    の一部を露出せしめて他を包みこんで封止する樹脂とを
    含むことを特徴とする半導体装置。
JP19211281U 1981-12-23 1981-12-23 半導体装置 Pending JPS5895655U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19211281U JPS5895655U (ja) 1981-12-23 1981-12-23 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19211281U JPS5895655U (ja) 1981-12-23 1981-12-23 半導体装置

Publications (1)

Publication Number Publication Date
JPS5895655U true JPS5895655U (ja) 1983-06-29

Family

ID=30105538

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19211281U Pending JPS5895655U (ja) 1981-12-23 1981-12-23 半導体装置

Country Status (1)

Country Link
JP (1) JPS5895655U (ja)

Similar Documents

Publication Publication Date Title
JPS5895655U (ja) 半導体装置
JPS602848U (ja) 半導体装置
JPS5822746U (ja) 半導体装置
JPS6064272U (ja) 半導体試験治具
JPS5889946U (ja) 半導体装置
JPS6113940U (ja) 半導体装置
JPS59107157U (ja) ＧａＡｓ半導体装置
JPS59164243U (ja) 樹脂封止半導体装置
JPS5889930U (ja) 半導体装置
JPS5844857U (ja) 半導体装置
JPS5881937U (ja) 半導体装置
JPS585347U (ja) 樹脂封止型半導体装置
JPS58177948U (ja) 樹脂封止半導体装置
JPS6068654U (ja) 半導体装置
JPS60163738U (ja) 半導体装置
JPS59191744U (ja) 半導体装置
JPS5878654U (ja) モ−ルド型半導体素子
JPS5944052U (ja) 半導体装置
JPS5844844U (ja) 半導体装置
JPS59189242U (ja) 樹脂封止半導体装置
JPS58433U (ja) 半導体装置
JPS605147U (ja) 半導体装置
JPS5834733U (ja) 半導体装置
JPS5981044U (ja) 半導体装置
JPS6096827U (ja) 熱伝導性半導体装置