JPS5981044U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS5981044U
JPS5981044U JP17687782U JP17687782U JPS5981044U JP S5981044 U JPS5981044 U JP S5981044U JP 17687782 U JP17687782 U JP 17687782U JP 17687782 U JP17687782 U JP 17687782U JP S5981044 U JPS5981044 U JP S5981044U
Authority
JP
Japan
Prior art keywords
semiconductor pellet
semiconductor
metal wire
semiconductor equipment
thin metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17687782U
Other languages
English (en)
Other versions
JPS6344992Y2 (ja
Inventor
米沢 啓四郎
Original Assignee
日本電気ホームエレクトロニクス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気ホームエレクトロニクス株式会社 filed Critical 日本電気ホームエレクトロニクス株式会社
Priority to JP17687782U priority Critical patent/JPS5981044U/ja
Publication of JPS5981044U publication Critical patent/JPS5981044U/ja
Application granted granted Critical
Publication of JPS6344992Y2 publication Critical patent/JPS6344992Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015Shape
    • H01L2924/10155Shape being other than a cuboid
    • H01L2924/10157Shape being other than a cuboid at the active surface

Landscapes

  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第1図は従来の半導体装置の要部断面図である。 第2図はこの考案の一実施例の半導体装置の要部断面図
である。 1・・・・・・放熱板、2・・・・・・ロウ材(半田)
、3・・・・・・半導体ベレット、4.5・・・・・・
上面電極、6.7・・・・・・リート、8,9・・・・
・・金属細線、10・・・・・・傾斜部、11・・・・
・・絶縁膜。

Claims (1)

    【実用新案登録請求の範囲】
  1. 放熱板上に半導体ベレットを固着し、半導体ベレットの
    上面電極を金属細線を介してリードに接続してなる半導
    体装置において、前記半導体ベレットの上部周縁部は傾
    斜部に形成され、この傾斜部に絶縁膜が形成されており
    、かつ半導体ベレットの上面電極とリードとを接続する
    金属細線かほぼ直線状に張架されていることを特徴とす
    る半導体装置。
JP17687782U 1982-11-22 1982-11-22 半導体装置 Granted JPS5981044U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17687782U JPS5981044U (ja) 1982-11-22 1982-11-22 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17687782U JPS5981044U (ja) 1982-11-22 1982-11-22 半導体装置

Publications (2)

Publication Number Publication Date
JPS5981044U true JPS5981044U (ja) 1984-05-31
JPS6344992Y2 JPS6344992Y2 (ja) 1988-11-22

Family

ID=30384428

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17687782U Granted JPS5981044U (ja) 1982-11-22 1982-11-22 半導体装置

Country Status (1)

Country Link
JP (1) JPS5981044U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007295012A (ja) * 2007-08-10 2007-11-08 Rohm Co Ltd 樹脂パッケージ型半導体装置の製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007295012A (ja) * 2007-08-10 2007-11-08 Rohm Co Ltd 樹脂パッケージ型半導体装置の製造方法
JP4666395B2 (ja) * 2007-08-10 2011-04-06 ローム株式会社 樹脂パッケージ型半導体装置の製造方法

Also Published As

Publication number Publication date
JPS6344992Y2 (ja) 1988-11-22

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