JPS58111958U - 半導体装置のリ−ドフレ−ム - Google Patents

半導体装置のリ−ドフレ−ム

Info

Publication number
JPS58111958U
JPS58111958U JP1982007298U JP729882U JPS58111958U JP S58111958 U JPS58111958 U JP S58111958U JP 1982007298 U JP1982007298 U JP 1982007298U JP 729882 U JP729882 U JP 729882U JP S58111958 U JPS58111958 U JP S58111958U
Authority
JP
Japan
Prior art keywords
lead frame
region
semiconductor devices
semiconductor chip
plating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1982007298U
Other languages
English (en)
Other versions
JPH0410699Y2 (ja
Inventor
信吾 藤井
桐山　博
雅己 長谷川
Original Assignee
シャープ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Priority to JP1982007298U priority Critical patent/JPS58111958U/ja
Publication of JPS58111958U publication Critical patent/JPS58111958U/ja
Application granted granted Critical
Publication of JPH0410699Y2 publication Critical patent/JPH0410699Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4823—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a pin of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は従来のリードフレームを示す平面図、第２図は
本考案による一実施例のリードフレームを示す平面図、
第３図は同実施例を用いた半導体装置の平面図である。 １１：リードフレーム、１−１ａ：第１リード、１１ｂ
＝第２リード、１２：銀メッキ膜、１３：錫メツキ膜、
１４：チップ、１５：ワイヤ、１６：樹脂。

Claims (1)

    【実用新案登録請求の範囲】
  1. 所望形状のリードが打抜かれた金属板の、半導体チップ
    をグイボンドする領域及び半導体チップに一端が接続さ
    れたワイヤの他端を接続する領域の夫々の平面に被着さ
    れた貴金属メッキ膜と、上記貴金属メッキ膜が被着され
    た領域から延びた金属板のアウターリード面に直ちに被
    着された半田−付性をもつ卑金属膜とを備えたことを特
    徴とする半導体装置のリードフレーム。
JP1982007298U 1982-01-21 1982-01-21 半導体装置のリ−ドフレ−ム Granted JPS58111958U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1982007298U JPS58111958U (ja) 1982-01-21 1982-01-21 半導体装置のリ−ドフレ−ム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1982007298U JPS58111958U (ja) 1982-01-21 1982-01-21 半導体装置のリ−ドフレ−ム

Publications (2)

Publication Number Publication Date
JPS58111958U true JPS58111958U (ja) 1983-07-30
JPH0410699Y2 JPH0410699Y2 (ja) 1992-03-17

Family

ID=30020054

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1982007298U Granted JPS58111958U (ja) 1982-01-21 1982-01-21 半導体装置のリ−ドフレ−ム

Country Status (1)

Country Link
JP (1) JPS58111958U (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10163519A (ja) * 1996-10-01 1998-06-19 Toshiba Corp 半導体装置及び半導体装置製造方法
JP2001230453A (ja) * 1999-12-08 2001-08-24 Nichia Chem Ind Ltd Ｌｅｄランプ及びその製造方法
JP2002094130A (ja) * 1999-01-05 2002-03-29 Nichia Chem Ind Ltd 発光ダイオード及びその製造方法、並びにそれを用いた表示装置

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51115775A (en) * 1975-04-04 1976-10-12 Nec Corp Semiconductor apparatus
JPS574183A (en) * 1980-06-10 1982-01-09 Toshiba Corp Metallic thin strip for installing semiconductor light-emitting element

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51115775A (en) * 1975-04-04 1976-10-12 Nec Corp Semiconductor apparatus
JPS574183A (en) * 1980-06-10 1982-01-09 Toshiba Corp Metallic thin strip for installing semiconductor light-emitting element

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10163519A (ja) * 1996-10-01 1998-06-19 Toshiba Corp 半導体装置及び半導体装置製造方法
JP2002094130A (ja) * 1999-01-05 2002-03-29 Nichia Chem Ind Ltd 発光ダイオード及びその製造方法、並びにそれを用いた表示装置
JP2001230453A (ja) * 1999-12-08 2001-08-24 Nichia Chem Ind Ltd Ｌｅｄランプ及びその製造方法

Also Published As

Publication number Publication date
JPH0410699Y2 (ja) 1992-03-17

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