JPS58184840U - 半導体装置 - Google Patents
半導体装置Info
- Publication number
- JPS58184840U JPS58184840U JP8115682U JP8115682U JPS58184840U JP S58184840 U JPS58184840 U JP S58184840U JP 8115682 U JP8115682 U JP 8115682U JP 8115682 U JP8115682 U JP 8115682U JP S58184840 U JPS58184840 U JP S58184840U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor equipment
- chip
- attached
- semiconductor
- chip carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Wire Bonding (AREA)
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
め要約のデータは記録されません。
Description
第１図は従来装置の構造断面図、第２図ａは本考案を適
用した半導体装置の構造断面図、第２図すはチップ担体
の平面概略図である。１は半導体チップ、２は導電ステ
ージ領域、３はパッケージ基体、４は導電配線層、５は
ボンデングワイヤ、６は外部リード端子、７はチップ担
体をそれぞれ示す。
用した半導体装置の構造断面図、第２図すはチップ担体
の平面概略図である。１は半導体チップ、２は導電ステ
ージ領域、３はパッケージ基体、４は導電配線層、５は
ボンデングワイヤ、６は外部リード端子、７はチップ担
体をそれぞれ示す。
Claims (1)
- 半導体チップをセラミックパッケージに収納する構造に
おいて、前記半導体チップを予めチップ担体に取りつけ
ワイヤボンデングした後、該チップ担体をセラミック基
体に取りつけたことを特徴とする半導体装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8115682U JPS58184840U (ja) | 1982-06-01 | 1982-06-01 | 半導体装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8115682U JPS58184840U (ja) | 1982-06-01 | 1982-06-01 | 半導体装置 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58184840U true JPS58184840U (ja) | 1983-12-08 |
Family
ID=30090277
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8115682U Pending JPS58184840U (ja) | 1982-06-01 | 1982-06-01 | 半導体装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58184840U (ja) |
-
1982
- 1982-06-01 JP JP8115682U patent/JPS58184840U/ja active Pending
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