JPS6127338U - 混成集積回路装置 - Google Patents

混成集積回路装置

Info

Publication number
JPS6127338U
JPS6127338U JP1984112326U JP11232684U JPS6127338U JP S6127338 U JPS6127338 U JP S6127338U JP 1984112326 U JP1984112326 U JP 1984112326U JP 11232684 U JP11232684 U JP 11232684U JP S6127338 U JPS6127338 U JP S6127338U
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit device
hybrid integrated
conductive paste
bonded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984112326U
Other languages
English (en)
Inventor
昭二 宮木
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP1984112326U priority Critical patent/JPS6127338U/ja
Publication of JPS6127338U publication Critical patent/JPS6127338U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】 第１図は本考案の一実施例の断面図である。 第２図は従来の混成集積回路装置の断面図。 １・・・回路基板、２・・・半導体チップ、３・・・導
電ペースト、４・・・配線導体、５・・・ボンディング
ワイヤ、６・・・プリコート樹脂、７・・・チップ部品
、８・・・接着樹脂、９・・・外部リード、１０・・・
はんだ。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体チップ及び部品の接着剤として導電ペーストを使
    用する混成集積回路装置において、チツ−ブ部品は、搭
    戚ランドと接する面のみ導電ペーストで接着され、その
    他の部分ははんだで接着されたことを特徴とする混成集
    積回路装置。
JP1984112326U 1984-07-24 1984-07-24 混成集積回路装置 Pending JPS6127338U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984112326U JPS6127338U (ja) 1984-07-24 1984-07-24 混成集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984112326U JPS6127338U (ja) 1984-07-24 1984-07-24 混成集積回路装置

Publications (1)

Publication Number Publication Date
JPS6127338U true JPS6127338U (ja) 1986-02-18

Family

ID=30671388

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984112326U Pending JPS6127338U (ja) 1984-07-24 1984-07-24 混成集積回路装置

Country Status (1)

Country Link
JP (1) JPS6127338U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04101738U (ja) * 1991-01-29 1992-09-02 三菱自動車エンジニアリング株式会社 リアゲートパネル用のダンパ取付装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04101738U (ja) * 1991-01-29 1992-09-02 三菱自動車エンジニアリング株式会社 リアゲートパネル用のダンパ取付装置

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