JPS60935U - 高電力混成集積回路 - Google Patents

高電力混成集積回路

Info

Publication number
JPS60935U
JPS60935U JP1983092971U JP9297183U JPS60935U JP S60935 U JPS60935 U JP S60935U JP 1983092971 U JP1983092971 U JP 1983092971U JP 9297183 U JP9297183 U JP 9297183U JP S60935 U JPS60935 U JP S60935U
Authority
JP
Japan
Prior art keywords
high power
hybrid integrated
integrated circuit
power hybrid
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1983092971U
Other languages
English (en)
Inventor
小「ざき」 良一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1983092971U priority Critical patent/JPS60935U/ja
Publication of JPS60935U publication Critical patent/JPS60935U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Details Of Resistors (AREA)
  • Cooling Or The Like Of Electrical Apparatus (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第1図は従来の構造、第2図は本考案の一実施例である
。図において2は発熱抵抗体、3は半導体素子、4はそ
の他の部品、5はヒートシンク、6は樹脂、11および
12は基板、13および14は端子、15は銀の小球を
示す。

Claims (1)

    【実用新案登録請求の範囲】
  1. 発熱抵抗体を搭載した基板にヒートシンクを固着し、該
    基板の端子と半導体素子やその他の部品を搭載した別基
    板の端子の間を、銀の小さい球を介して半田で接続する
    ことを特徴とする高電力混成集積回路。
JP1983092971U 1983-06-17 1983-06-17 高電力混成集積回路 Pending JPS60935U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983092971U JPS60935U (ja) 1983-06-17 1983-06-17 高電力混成集積回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983092971U JPS60935U (ja) 1983-06-17 1983-06-17 高電力混成集積回路

Publications (1)

Publication Number Publication Date
JPS60935U true JPS60935U (ja) 1985-01-07

Family

ID=30223474

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983092971U Pending JPS60935U (ja) 1983-06-17 1983-06-17 高電力混成集積回路

Country Status (1)

Country Link
JP (1) JPS60935U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6379673A (ja) * 1986-09-24 1988-04-09 今永 栄輔 飲用静電治療器

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6379673A (ja) * 1986-09-24 1988-04-09 今永 栄輔 飲用静電治療器

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