JPS59145047U - 半導体装置 - Google Patents
半導体装置Info
- Publication number
- JPS59145047U JPS59145047U JP1983038962U JP3896283U JPS59145047U JP S59145047 U JPS59145047 U JP S59145047U JP 1983038962 U JP1983038962 U JP 1983038962U JP 3896283 U JP3896283 U JP 3896283U JP S59145047 U JPS59145047 U JP S59145047U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- semiconductor equipment
- abstract
- semiconductor device
- bonding wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
Landscapes
- Wire Bonding (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
め要約のデータは記録されません。
Description
第1図a、 bは従来の半導体装置の斜視図および断
面図、第2図は本考案の一実施例の断面図である。 1・・・ベースリボンアイランド、2・・・リード、3
・・・ICチップ、4.7・・・ボンデ−イングワイヤ
、5・・・第1のICチップ、6・・・第2のICチッ
プ。 。
面図、第2図は本考案の一実施例の断面図である。 1・・・ベースリボンアイランド、2・・・リード、3
・・・ICチップ、4.7・・・ボンデ−イングワイヤ
、5・・・第1のICチップ、6・・・第2のICチッ
プ。 。
Claims (1)
- 第1のICチップと、この第1のICチップの上に重ね
て固定され、さらに前記第1のICチップと共通な電極
同志がホンディングワイヤにより接続された第2のIC
チップとを備えたことを特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1983038962U JPS59145047U (ja) | 1983-03-17 | 1983-03-17 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1983038962U JPS59145047U (ja) | 1983-03-17 | 1983-03-17 | 半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59145047U true JPS59145047U (ja) | 1984-09-28 |
Family
ID=30169623
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1983038962U Pending JPS59145047U (ja) | 1983-03-17 | 1983-03-17 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59145047U (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03116860A (ja) * | 1989-09-29 | 1991-05-17 | Hitachi Ltd | 半導体装置 |
JPH0575017A (ja) * | 1991-01-02 | 1993-03-26 | Honeywell Inc | 直接式マイクロ回路の減結合装置 |
-
1983
- 1983-03-17 JP JP1983038962U patent/JPS59145047U/ja active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03116860A (ja) * | 1989-09-29 | 1991-05-17 | Hitachi Ltd | 半導体装置 |
JPH0575017A (ja) * | 1991-01-02 | 1993-03-26 | Honeywell Inc | 直接式マイクロ回路の減結合装置 |
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