JPS58111959U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS58111959U
JPS58111959U JP1982007299U JP729982U JPS58111959U JP S58111959 U JPS58111959 U JP S58111959U JP 1982007299 U JP1982007299 U JP 1982007299U JP 729982 U JP729982 U JP 729982U JP S58111959 U JPS58111959 U JP S58111959U
Authority
JP
Japan
Prior art keywords
semiconductor chip
wire
noble metal
film
semiconductor equipment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1982007299U
Other languages
English (en)
Inventor
信吾 藤井
桐山　博
雅己 長谷川
Original Assignee
シャープ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Priority to JP1982007299U priority Critical patent/JPS58111959U/ja
Publication of JPS58111959U publication Critical patent/JPS58111959U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4823—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a pin of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
、　　第１図は従来のリードフレームを示す平面図、第
２図は本考案による一実施例のリードフレームを示す平
面図、第３図は同実施例を用いた半導体装置の平面図で
ある。 １１：リードフレーム、１１ａ：第１リード、１１ｂ：
第２リード、１２：銀メッキ膜、１３：錫メ　　　′ツ
キ膜、１４：チップ、１５：ワイヤ、１６：樹脂。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体チップを塔載する表面及びワイヤの一端を接続す
    る表面に夫々貴金属メッキ膜が形成され、アウターリー
    ド表面に半田付性の良好な卑金属膜が形成されたリード
    フレームと、該リードフレームの貴金属メッキ膜部分に
    ボンディングされた半一導体チップと、半導体チップ上
    の電極と上記ＩＪ＝ドフレームの他の貴金属メッキ膜部
    分にボンディングされたワイヤと、上記半導体チップ及
    びワイヤを封止する樹脂とを備えてなる半導体装置。
JP1982007299U 1982-01-21 1982-01-21 半導体装置 Pending JPS58111959U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1982007299U JPS58111959U (ja) 1982-01-21 1982-01-21 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1982007299U JPS58111959U (ja) 1982-01-21 1982-01-21 半導体装置

Publications (1)

Publication Number Publication Date
JPS58111959U true JPS58111959U (ja) 1983-07-30

Family

ID=30020055

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1982007299U Pending JPS58111959U (ja) 1982-01-21 1982-01-21 半導体装置

Country Status (1)

Country Link
JP (1) JPS58111959U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10163519A (ja) * 1996-10-01 1998-06-19 Toshiba Corp 半導体装置及び半導体装置製造方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS574183A (en) * 1980-06-10 1982-01-09 Toshiba Corp Metallic thin strip for installing semiconductor light-emitting element

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS574183A (en) * 1980-06-10 1982-01-09 Toshiba Corp Metallic thin strip for installing semiconductor light-emitting element

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10163519A (ja) * 1996-10-01 1998-06-19 Toshiba Corp 半導体装置及び半導体装置製造方法

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