JPS5978542A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JPS5978542A
JPS5978542A JP57187387A JP18738782A JPS5978542A JP S5978542 A JPS5978542 A JP S5978542A JP 57187387 A JP57187387 A JP 57187387A JP 18738782 A JP18738782 A JP 18738782A JP S5978542 A JPS5978542 A JP S5978542A
Authority
JP
Japan
Prior art keywords
film
deposited
groove
substrate
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57187387A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0586659B2 (enExample
Inventor
Kohei Ebara
江原　孝平
Susumu Muramoto
村本　進
Seitaro Matsuo
松尾　誠太郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP57187387A priority Critical patent/JPS5978542A/ja
Publication of JPS5978542A publication Critical patent/JPS5978542A/ja
Publication of JPH0586659B2 publication Critical patent/JPH0586659B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Landscapes

  • Local Oxidation Of Silicon (AREA)
  • Drying Of Semiconductors (AREA)
  • Element Separation (AREA)
JP57187387A 1982-10-27 1982-10-27 半導体装置の製造方法 Granted JPS5978542A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57187387A JPS5978542A (ja) 1982-10-27 1982-10-27 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57187387A JPS5978542A (ja) 1982-10-27 1982-10-27 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS5978542A true JPS5978542A (ja) 1984-05-07
JPH0586659B2 JPH0586659B2 (enExample) 1993-12-13

Family

ID=16205124

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57187387A Granted JPS5978542A (ja) 1982-10-27 1982-10-27 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS5978542A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02125444A (ja) * 1988-07-05 1990-05-14 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JP2008060517A (ja) * 2006-08-29 2008-03-13 Samsung Electronics Co Ltd マスク構造物の形成方法及びこれを利用した微細パターン形成方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5669833A (en) * 1979-11-09 1981-06-11 Toshiba Corp Fine processing method of thin film
JPS56131945A (en) * 1980-03-19 1981-10-15 Matsushita Electric Ind Co Ltd Forming method of silicon oxidation film
JPS56137651A (en) * 1980-03-17 1981-10-27 Ibm Method of forming exfoliating region
JPS56142667A (en) * 1980-03-13 1981-11-07 Ibm Semiconductor device
JPS5864044A (ja) * 1981-10-14 1983-04-16 Toshiba Corp 半導体装置の製造方法
JPS5919349A (ja) * 1982-07-26 1984-01-31 Toshiba Corp 半導体装置およびその製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5669833A (en) * 1979-11-09 1981-06-11 Toshiba Corp Fine processing method of thin film
JPS56142667A (en) * 1980-03-13 1981-11-07 Ibm Semiconductor device
JPS56137651A (en) * 1980-03-17 1981-10-27 Ibm Method of forming exfoliating region
JPS56131945A (en) * 1980-03-19 1981-10-15 Matsushita Electric Ind Co Ltd Forming method of silicon oxidation film
JPS5864044A (ja) * 1981-10-14 1983-04-16 Toshiba Corp 半導体装置の製造方法
JPS5919349A (ja) * 1982-07-26 1984-01-31 Toshiba Corp 半導体装置およびその製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02125444A (ja) * 1988-07-05 1990-05-14 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JP2008060517A (ja) * 2006-08-29 2008-03-13 Samsung Electronics Co Ltd マスク構造物の形成方法及びこれを利用した微細パターン形成方法

Also Published As

Publication number Publication date
JPH0586659B2 (enExample) 1993-12-13

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